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Verified 2026-10

arduino R7FA4M1AB3CFM UNO R4 Minima

UNO-form-factor 5 V board on a 48 MHz Renesas R7FA4M1AB3CFM with 256 kB flash, 32 kB RAM, a 14-bit ADC, a 12-bit DAC on A0, CAN and an ICSP plus SWD/JTAG header, drawing about 33 mA on USB-C - 22.00 EUR as measured.

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Logic level5 V

Part & documents

Headline partR7FA4M1AB3CFM
Data sheetR7FA4M1AB3CFM data sheet →
Sourcestore.arduino.cc/products/uno-r4-minima →

Specs

MCURenesas R7FA4M1AB3CFM#AA0 (Arm Cortex-M4 at 48 MHz with FPU, 256 kB flash, 32 kB SRAM, 8 kB data flash, 14-bit ADC, 12-bit DAC, OPAMP, CAN)
Clock48 MHz
RAM32 KB

Pinout

48 pads, as the vendor numbers them.

#NameFunctionSignals
1BOOTAnalog-side header JANALOG pad 1: BOOT - Mode selection. Pad 1 of the analog header carries BOOT, the mode-selection line.BOOT, mode
2IOREFAnalog-side header JANALOG pad 2: IOREF - Reference for digital logic V - connected to 5 V. IOREF is a reference, not a supply - the datasheet describes it as the reference for digital logic, connected to the 5 V rail.IOREF, ioref
3ResetAnalog-side header JANALOG pad 3: Reset - ResetReset, reset
4+3V3Analog-side header JANALOG pad 4: +3V3 - +3V3 Power Rail. The +3V3 pin is the only 3.3 V contact on the board and it draws from the RA4M1's VCC_USB pin, not from the buck converter - the datasheet says so explicitly.+3V3, power
5+5VAnalog-side header JANALOG pad 5: +5V - +5V Power Rail. 5 V comes either from the USB-C port (about 4.7 V after the Schottky drop) or from the ISL854102FRZ buck converter when VIN or the DC jack is powered.+5V, power
6GNDAnalog-side header JANALOG pad 6: GND - GroundGND, power
7GNDAnalog-side header JANALOG pad 7: GND - GroundGND, power
8VINAnalog-side header JANALOG pad 8: VIN - Voltage Input. VIN accepts 6-24 V and feeds the ISL854102FRZ buck converter, which steps it down to 5 V; the barrel jack sits on the same node.VIN, power
9A0Analog-side header JANALOG pad 9: A0 - Analog input 0 / DAC. A0 is also the output of the RA4M1's DAC, up to 12-bit resolution.A0
10A1Analog-side header JANALOG pad 10: A1 - Analog input 1 / OPAMP+. A1 is also the non-inverting input of the RA4M1 operational amplifier (OPAMP+).A1
11A2Analog-side header JANALOG pad 11: A2 - Analog input 2 / OPAMP-. A2 is also the inverting input of the on-chip operational amplifier (OPAMP-).A2
12A3Analog-side header JANALOG pad 12: A3 - Analog input 3 / OPAMPOut. A3 is also the on-chip operational amplifier's output (OPAMPOut).A3
13A4Analog-side header JANALOG pad 13: A4 - Analog input 4 / I²C Serial Datal (SDA). A4 is the I2C data line (SDA) and the pinout poster prints it as D18/SDA; the poster warns that A4 and A5 are the same pins as D18/SDA and D19/SCL and only one peripheral can use them at a time.A4
14A5Analog-side header JANALOG pad 14: A5 - Analog input 5 / I²C Serial Clock (SCL). A5 is the I2C clock line (SCL) and the pinout poster prints it as D19/SCL.A5
15SCLDigital-side header JDIGITAL pad 1: SCL - I²C Serial Clock (SCL). SCL on the digital header is the same net as A5 (printed D19/SCL on the poster).SCL
16SDADigital-side header JDIGITAL pad 2: SDA - I²C Serial Datal (SDA). SDA on the digital header is the same net as A4 (printed D18/SDA on the poster).SDA
17AREFDigital-side header JDIGITAL pad 3: AREF - Analog Reference Voltage. AREF is the ADC's external reference input; VDD (the 5 V rail) sets the default full scale and the logic level.AREF
18GNDDigital-side header JDIGITAL pad 4: GND - GroundGND, power
19D13/SCKDigital-side header JDIGITAL pad 5: D13/SCK - GPIO 13 / SPI Clock. D13 is the SPI clock and is also ICSP pad 3 - the poster says the SPI connector pins are shared with the digital header.D13, SCK
20D12/CIPODigital-side header JDIGITAL pad 6: D12/CIPO - GPIO 12 / SPI Controller In Peripheral Out. D12 is SPI CIPO (formerly MISO) and is ICSP pad 1.D12, CIPO
21D11/COPIDigital-side header JDIGITAL pad 7: D11/COPI - GPIO 11 (PWM) / SPI Controller Out Peripheral In. D11 is SPI COPI (formerly MOSI), PWM-capable, and is ICSP pad 4.D11, COPI
22D10/CSDigital-side header JDIGITAL pad 8: D10/CS - GPIO 10 (PWM) / SPI Chip Select. D10 is SPI chip select, PWM-capable, and shares the ICSP SPI bus.D10, CS
23D9Digital-side header JDIGITAL pad 9: D9 - GPIO 9 (PWM~)D9
24D8Digital-side header JDIGITAL pad 10: D8 - GPIO 8D8
25D7Digital-side header JDIGITAL pad 11: D7 - GPIO 7D7
26D6Digital-side header JDIGITAL pad 12: D6 - GPIO 6 (PWM~)D6
27D5/CANRX0Digital-side header JDIGITAL pad 13: D5/CANRX0 - GPIO 5 (PWM~) / CAN Transmitter (TX). D5 is labelled D5/CANRX0 while its own description reads 'CAN Transmitter (TX)' - the label and the description disagree on this pad.D5, CANRX0
28D4/CANTX0Digital-side header JDIGITAL pad 14: D4/CANTX0 - GPIO 4 / CAN Receiver (RX). D4 is labelled D4/CANTX0 while its own description reads 'CAN Receiver (RX)' - the label and the description disagree on this pad.D4, CANTX0
29D3Digital-side header JDIGITAL pad 15: D3 - GPIO 3 (PWM~) / Interrupt PinD3
30D2Digital-side header JDIGITAL pad 16: D2 - GPIO 2 / Interrupt PinD2
31D1/TX0Digital-side header JDIGITAL pad 17: D1/TX0 - GPIO 1 / Serial 0 Transmitter (TX). D1 is serial transmit on the hardware UART; the same serial interface is the one the USB-C port exposes.D1, TX0
32D0/TX0Digital-side header JDIGITAL pad 18: D0/TX0 - GPIO 0 / Serial 0 Receiver (RX). D0 is serial receive. The vendor table prints the label as D0/TX0 while its description reads 'Serial 0 Receiver (RX)' - label and description disagree.D0, TX0
33CIPOICSP header J1 pad 1: CIPO - Controller In Peripheral Out. CIPO on ICSP is D12's net.CIPO, internal
34+5VICSP header J1 pad 2: +5V - Power Supply of 5 V. ICSP supplies 5 V here.+5V, internal
35SCKICSP header J1 pad 3: SCK - Serial Clock. SCK on ICSP is D13's net.SCK, internal
36COPIICSP header J1 pad 4: COPI - Controller Out Peripheral In. COPI on ICSP is D11's net.COPI, internal
37RESETICSP header J1 pad 5: RESET - Reset. RESET is the RA4M1 reset line, the same one the reset button drives.RESET, internal
38GNDICSP header J1 pad 6: GND - GroundGND, internal
39+5VSWD/JTAG header J2 pad 1: +5V - Power Supply of 5 V+5V, internal
40SWDIOSWD/JTAG header J2 pad 2: SWDIO - Data I/O pinSWDIO, internal
41GNDSWD/JTAG header J2 pad 3: GND - GroundGND, internal
42SWCLKSWD/JTAG header J2 pad 4: SWCLK - Clock PinSWCLK, internal
43GNDSWD/JTAG header J2 pad 5: GND - GroundGND, internal
44NCSWD/JTAG header J2 pad 6: NC - Not connectedNC, internal
45RXSWD/JTAG header J2 pad 7: RX - Serial Receiver. The SWD/JTAG header breaks out the RA4M1's SCI_RXD1 serial receiver.RX, internal
46TXSWD/JTAG header J2 pad 8: TX - Serial Transmitter. The SWD/JTAG header breaks out the RA4M1's SCI_TXD1 serial transmitter.TX, internal
47GNDSWD/JTAG header J2 pad 9: GND - GroundGND, internal
48NCSWD/JTAG header J2 pad 10: NC - Not connectedNC, internal

Buses

BusSignalsPinsVoltageNote
I2C ×1SDA, SCLA4, A55 V VOne bus on A4 (SDA) and A5 (SCL), repeated on the digital header as SDA and SCL, with no on-board device, so no addresses. The pinout poster warns A4/A5 are the same pins as D18/SDA and D19/SCL and only one peripheral can use them at a time.
SPI ×1SCK, CIPO, COPI, CSD13/SCK, D12/CIPO, D11/COPI, D10/CS5 V VOne SPI bus on D13 (SCK), D12 (CIPO, formerly MISO), D11 (COPI, formerly MOSI) and D10 (CS); the ICSP header's pads 1, 3 and 4 are the same nets, which the poster states explicitly.
UART ×1TX, RXD1/TX0, D0/TX05 V VOne hardware UART on D0 (RX) and D1 (TX); the USB-C port exposes the same serial interface, and the SWD/JTAG header breaks out SCI_RXD1/SCI_TXD1 on its pads 7 and 8.
CAN ×1CANRX0, CANTX0D5/CANRX0, D4/CANTX05 V VThe datasheet's feature list and its digital table agree that CAN is on D4/D5, but the table's labels and its own descriptions are swapped (D5 labelled CANRX0 and described as the transmitter, D4 labelled CANTX0 and described as the receiver); recorded unresolved. An external transceiver is required.

Power

Input6-24 V on VIN or the barrel jack (buck-converted to 5 V by the ISL854102FRZ), or 4.8-5.5 V on USB-C
Input rangeVIN 6 V min, 7.0 V typ, 24 V max; VUSB 4.8 V min, 5.0 V typ, 5.5 V max
Typical draw33.39 mA

Average current consumption on USB-C running the shipped blink firmware: 29.71 mA min, 33.39 mA typ, 36.98 mA max. GPIO current is 8 mA per pin and the pinout poster adds a 60 mA maximum overall for the MCU.

Outputs

RailRatingNote
+5V5 V VThe board's logic rail, from USB (about 4.7 V after the Schottky drop) or from the ISL854102FRZ buck converter; brought out on JANALOG pad 5 and on ICSP pad 2.
+3V33.3 V VBrought out on JANALOG pad 4 only. The datasheet says this pin draws power from the RA4M1's VCC_USB pin and is not connected to the buck converter, so it is not a general-purpose 3.3 V rail.

Notes

Two headers numbered from 1 by the vendor (JANALOG 1-14, JDIGITAL 1-18), plus ICSP and the SWD/JTAG header, are folded into this entry's single 1-48 sequence with the connector and the vendor's own pad number named in every description. Every label comes from the datasheet's pin tables (10.1-10.4), parsed as text rather than read off the drawing. The SWD/JTAG header's last two pads are marked NC by the vendor and are kept because they are real contacts on the land pattern. Arduino's digital table swaps the CANRX0/CANTX0 labels against their descriptions and labels the D0 pad TX0 while describing it as receive; both are recorded unresolved. Arduino sells this board at 22.00 EUR as measured by this campaign's fetcher; the currency is as returned, not converted.

AI context

Dense context for pasting into a model prompt — addresses, pinout, voltages, tolerances and the vendor's reference circuit.

PART: Arduino UNO R4 Minima, SKU ABX00080, a UNO-form-factor board built around the Renesas R7FA4M1AB3CFM#AA0 (Arm Cortex-M4 with FPU at 48 MHz, 256 kB flash, 32 kB SRAM, 8 kB data flash used as EEPROM, up to 14-bit ADC, up to 12-bit DAC, on-chip OPAMP, capacitive touch unit, USB 2.0 full-speed, CAN controller). No radio and no second MCU: the board is the RA4M1, the ISL854102FRZ buck converter, a 3.3 V regulator path from the MCU's own VCC_USB pin, the header set, ICSP, a SWD/JTAG header, a USB-C port, a DC jack and a reset button. Arduino rates it at 29.71 mA minimum, 33.39 mA typical and 36.98 mA maximum average consumption on USB-C running the shipped blink firmware.
PINOUT: Arduino numbers each header from 1, so no two connectors share a sequence here: JANALOG pads 1-14, JDIGITAL pads 1-18, ICSP pads 1-6 and an SWD/JTAG header with pads 1-10. This entry numbers JANALOG 1-14, JDIGITAL 15-32, ICSP J1 33-38 and the SWD/JTAG header J2 39-48, and every description names its connector and the vendor's own pad number, the same offset convention the Nano R4 entry uses. JANALOG 1-14: BOOT, IOREF, Reset, +3V3, +5V, GND, GND, VIN, A0, A1, A2, A3, A4, A5. JDIGITAL 1-18 in this entry's order (15-32): SCL, SDA, AREF, GND, D13/SCK, D12/CIPO, D11/COPI, D10/CS, D9, D8, D7, D6, D5/CANRX0, D4/CANTX0, D3, D2, D1/TX0, D0. The pinout poster prints the SCL and SDA pads as D19/SCL and D18/SDA, the same nets as A5 and A4.. I2C: one bus, 5 V, on A4 (SDA) and A5 (SCL) with the same two nets repeated on the digital header as SDA and SCL, and no I2C device on the board, so there are no addresses. The pinout poster warns that A4/A5 are the same pins as D18/SDA and D19/SCL and that only one peripheral can use them at a time.
SUPPLY: VIN takes 6 V minimum, 7.0 V typical, 24 V maximum from the VIN pad or the barrel jack, and the ISL854102FRZ buck converter drops it to 5 V; USB-C takes 4.8-5.5 V and about 4.7 V reaches the MCU after the Schottky drop. VDD, and therefore the logic level, is the 5 V rail; VAREF is the analog reference, brought out on AREF.
LOGIC LEVEL: the datasheet states the whole board runs at 5 V except the +3V3 pin, which draws from the RA4M1's VCC_USB pin rather than from the buck converter - it is a tap, not a supply rail. GPIO current is 8 mA per pin, and the full-pinout poster adds a 60 mA maximum overall for the MCU.
REFERENCE CIRCUIT: the datasheet publishes no I2C pull-up values, no decoupling values and no external-component circuit for this board, so none are recorded here; there is no level translator and no second MCU to wire around.
TRAPS: (1) The ICSP header is not an independent port - its CIPO, SCK and COPI pads are D12, D13 and D11, and the poster says so. (2) CAN is stated twice and inconsistently: the feature list says D4/D5, and the digital table agrees on the pad numbers but swaps the labels against their own descriptions (D5 is labelled CANRX0 and described as the transmitter, D4 is labelled CANTX0 and described as the receiver); an external transceiver is required either way. (3) The pad labelled D0/TX0 is described by the vendor as 'Serial 0 Receiver (RX)' - label and description disagree. (4) The 3.3 V pin cannot be treated as a general 3.3 V rail; it is the MCU's VCC_USB pin. (5) Double-tapping reset enters the bootloader if a sketch has locked the board out of USB.

Provenance

Every figure on this page was read from the 4 sources below and last checked on Oct 27, 2026.