arduino R7FA4M1AB3CFM UNO R4 WiFi — pinout, specs

Part & documents

Headline part	R7FA4M1AB3CFM
Data sheet	R7FA4M1AB3CFM data sheet →
Source	store.arduino.cc/products/uno-r4-wifi →

Specs

MCU	Renesas R7FA4M1AB3CFM#AA0 (Arm Cortex-M4 at 48 MHz with FPU, 256 kB flash, 32 kB SRAM, 8 kB data flash, 14-bit ADC, 12-bit DAC, OPAMP, CAN) plus Espressif ESP32-S3-MINI-1-N8 (dual-core LX7 at 3.3 V, 384 kB ROM, 512 kB SRAM, Wi-Fi 4, Bluetooth 5)
Clock	48 MHz
RAM	32 KB

Pinout

47 pads, as the vendor numbers them.

#	Name	Function	Signals
1	BOOT	Analog-side header JANALOG pad 1: BOOT - Mode selection. Pad 1 of the analog header carries BOOT, the mode-selection line.	BOOT, mode
2	IOREF	Analog-side header JANALOG pad 2: IOREF - Reference for digital logic V - connected to 5 V. IOREF is a reference, not a supply - the datasheet describes it as the reference for digital logic, connected to the 5 V rail.	IOREF, ioref
3	Reset	Analog-side header JANALOG pad 3: Reset - Reset	Reset, reset
4	+3V3	Analog-side header JANALOG pad 4: +3V3 - +3V3 Power Rail. The 3.3 V rail comes from the SGM2205-3.3XKC3G/TR linear regulator fed by the 5 V rail, and it is the rail the ESP32-S3 module runs on.	+3V3, power
5	+5V	Analog-side header JANALOG pad 5: +5V - +5V Power Rail. 5 V comes either from the USB-C port (about 4.7 V after the Schottky drop) or from the ISL854102FRZ buck converter when VIN is powered.	+5V, power
6	GND	Analog-side header JANALOG pad 6: GND - Ground	GND, power
7	GND	Analog-side header JANALOG pad 7: GND - Ground	GND, power
8	VIN	Analog-side header JANALOG pad 8: VIN - Voltage Input. VIN accepts 6-24 V and feeds the ISL854102FRZ buck converter, which steps it down to 5 V.	VIN, power
9	A0	Analog-side header JANALOG pad 9: A0 - Analog input 0 / DAC. A0 is also the output of the RA4M1's DAC, up to 12-bit resolution.	A0
10	A1	Analog-side header JANALOG pad 10: A1 - Analog input 1 / OPAMP+. A1 is also the non-inverting input of the RA4M1 operational amplifier (OPAMP+).	A1
11	A2	Analog-side header JANALOG pad 11: A2 - Analog input 2 / OPAMP-. A2 is also the inverting input of the on-chip operational amplifier (OPAMP-).	A2
12	A3	Analog-side header JANALOG pad 12: A3 - Analog input 3 / OPAMPOut. A3 is also the on-chip operational amplifier's output (OPAMPOut).	A3
13	A4	Analog-side header JANALOG pad 13: A4 - Analog input 4 / I2C Serial Datal (SDA). A4 is the main I2C bus data line (Wire) and the pinout poster prints it as D18/SDA. Arduino states A4 and A5 must not be used as ADC inputs while the main bus is in use.	A4
14	A5	Analog-side header JANALOG pad 14: A5 - Analog input 5 / I2C Serial Clock (SCL). A5 is the main I2C bus clock line (Wire) and the pinout poster prints it as D19/SCL. Arduino states A4 and A5 must not be used as ADC inputs while the main bus is in use.	A5
15	SCL	Digital-side header JDIGITAL pad 1: SCL - I2C Serial Clock (SCL). SCL on the digital header is the same net as A5; the poster prints it D19/SCL and notes that only one peripheral can use the shared pin at a time.	SCL
16	SDA	Digital-side header JDIGITAL pad 2: SDA - I2C Serial Datal (SDA). SDA on the digital header is the same net as A4; the poster prints it D18/SDA and notes that only one peripheral can use the shared pin at a time.	SDA
17	AREF	Digital-side header JDIGITAL pad 3: AREF - Analog Reference Voltage. AREF is the ADC's external reference input; VDD (the 5 V rail) sets the default full scale and the logic level.	AREF
18	GND	Digital-side header JDIGITAL pad 4: GND - Ground	GND, power
19	D13/SCK/CANRX0	Digital-side header JDIGITAL pad 5: D13/SCK/CANRX0 - GPIO 13 / SPI Clock / CAN Receiver (RX). D13 doubles as the SPI clock and, per the datasheet's digital table, CAN receive (CANRX0); the ICSP header's SCK pin is the same net.	D13, SCK, CANRX0
20	D12/CIPO	Digital-side header JDIGITAL pad 6: D12/CIPO - GPIO 12 / SPI Controller In Peripheral Out. D12 is SPI Controller In Peripheral Out (CIPO, the pin formerly called MISO) and is shared with ICSP pad 1.	D12, CIPO
21	D11/COPI	Digital-side header JDIGITAL pad 7: D11/COPI - GPIO 11 (PWM) / SPI Controller Out Peripheral In. D11 is SPI Controller Out Peripheral In (COPI, formerly MOSI), PWM-capable, and shared with ICSP pad 4.	D11, COPI
22	D10/CS/CANTX0	Digital-side header JDIGITAL pad 8: D10/CS/CANTX0 - GPIO 10 (PWM) / SPI Chip Select / CAN Transmitter (TX). D10 is SPI chip select, PWM-capable, and the datasheet's digital table also gives it CAN transmit (CANTX0).	D10, CS, CANTX0
23	D9	Digital-side header JDIGITAL pad 9: D9 - GPIO 9 (PWM~)	D9
24	D8	Digital-side header JDIGITAL pad 10: D8 - GPIO 8	D8
25	D7	Digital-side header JDIGITAL pad 11: D7 - GPIO 7	D7
26	D6	Digital-side header JDIGITAL pad 12: D6 - GPIO 6 (PWM~)	D6
27	D5	Digital-side header JDIGITAL pad 13: D5 - GPIO 5 (PWM~)	D5
28	D4	Digital-side header JDIGITAL pad 14: D4 - GPIO 4	D4
29	D3	Digital-side header JDIGITAL pad 15: D3 - GPIO 3 (PWM~) / Interrupt Pin	D3
30	D2	Digital-side header JDIGITAL pad 16: D2 - GPIO 2 / Interrupt Pin	D2
31	D1/TX0	Digital-side header JDIGITAL pad 17: D1/TX0 - GPIO 1 / Serial 0 Transmitter (TX). D1 is serial transmit on the hardware UART; the same serial interface is the one the USB-C port exposes.	D1, TX0
32	D0/TX0	Digital-side header JDIGITAL pad 18: D0/TX0 - GPIO 0 / Serial 0 Receiver (RX). D0 is serial receive. The vendor table prints the label as D0/TX0 while its own description reads 'Serial 0 Receiver (RX)' - the label and the description disagree on this pad.	D0, TX0
33	OFF	JOFF header pad 1: OFF - For controlling power supply. OFF controls the board's power supply; the vendor numbers the OFF pair 1-2 and the VRTC pad separately as pin 1 of the same JOFF header.	OFF, power
34	GND	JOFF header pad 2: GND - Ground	GND, power
35	VRTC	JOFF header pad 1: VRTC - Battery connection to power RTC only. OFF controls the board's power supply; the vendor numbers the OFF pair 1-2 and the VRTC pad separately as pin 1 of the same JOFF header.	VRTC, power
36	CIPO	ICSP header J3 pad 1: CIPO - Controller In Peripheral Out. CIPO on ICSP is D12's net.	CIPO, internal
37	+5V	ICSP header J3 pad 2: +5V - Power Supply of 5 V. ICSP supplies 5 V here.	+5V, internal
38	SCK	ICSP header J3 pad 3: SCK - Serial Clock. SCK on ICSP is D13's net.	SCK, internal
39	COPI	ICSP header J3 pad 4: COPI - Controller Out Peripheral In. COPI on ICSP is D11's net.	COPI, internal
40	RESET	ICSP header J3 pad 5: RESET - Reset. RESET is the RA4M1 reset line, the same one the reset button drives.	RESET, internal
41	GND	ICSP header J3 pad 6: GND - Ground	GND, internal
42	ESP_IO42	ESP header J6 pad 1: ESP_IO42 - MTMS debugging. These are 3.3 V ESP32-S3 pins, not the RA4M1's 5 V pins.	ESP32-S3 header, 3.3 V logic
43	ESP_IO41	ESP header J6 pad 2: ESP_IO41 - MTDI debugging. These are 3.3 V ESP32-S3 pins, not the RA4M1's 5 V pins.	ESP32-S3 header, 3.3 V logic
44	ESP_TXD0	ESP header J6 pad 3: ESP_TXD0 - serial transmit (UART). These are 3.3 V ESP32-S3 pins, not the RA4M1's 5 V pins.	ESP32-S3 header, 3.3 V logic
45	ESP_DOWNLOAD	ESP header J6 pad 4: ESP_DOWNLOAD - boot mode. These are 3.3 V ESP32-S3 pins, not the RA4M1's 5 V pins.	ESP32-S3 header, 3.3 V logic
46	ESP_RXD0	ESP header J6 pad 5: ESP_RXD0 - serial receive (UART). These are 3.3 V ESP32-S3 pins, not the RA4M1's 5 V pins.	ESP32-S3 header, 3.3 V logic
47	GND	ESP header J6 pad 6: GND - ground. These are 3.3 V ESP32-S3 pins, not the RA4M1's 5 V pins.	ESP32-S3 header, ground

Buses

Bus	Signals	Pins	Voltage	Note
I2C ×2	SDA, SCL	A4, A5	5 V on A4/A5 and the digital-header SDA/SCL pads, 3.3 V on the Qwiic connector V	Two buses, no on-board device, so no addresses. The main bus is Wire on A4 (SDA) and A5 (SCL), repeated on the digital header; the secondary bus is I2C0 as Wire1 on the Qwiic JST-SH socket at 3.3 V. Arduino says A4/A5 must not be used as ADC inputs while the main bus is in use, and both sets of pads may be used at once.
SPI ×1	SCK, CIPO, COPI, CS	D13/SCK/CANRX0, D12/CIPO, D11/COPI, D10/CS/CANTX0	5 V V	One SPI bus on D13 (SCK), D12 (CIPO, formerly MISO), D11 (COPI, formerly MOSI) and D10 (CS), all repeated on the ICSP header as its pads 1, 3 and 4.
UART ×1	TX, RX	D1/TX0, D0/TX0	5 V V	One hardware UART on D0 (RX) and D1 (TX); the USB-C port exposes the same serial interface.
CAN ×1	CANRX0, CANTX0	D13/SCK/CANRX0, D10/CS/CANTX0	5 V V	The digital pin table gives CAN receive on D13 and CAN transmit on D10, while the datasheet's own feature list says D4/D5; the disagreement is recorded, not resolved. An external transceiver is required.

Power

Input	6-24 V on VIN or the DC jack (buck-converted to 5 V by the ISL854102FRZ), or 4.8-5.5 V on USB-C
Input range	VIN 6 V min, 7.0 V typ, 24 V max; VUSB 4.8 V min, 5.0 V typ, 5.5 V max

GPIO current limit is 8 mA per pin on the R7FA4M1AB3CFM; Arduino states the datasheet publishes no board-wide total for this model.

Outputs

Rail	Rating	Note
+5V	5 V V	The board's logic rail, from USB (about 4.7 V after the Schottky drop) or from the ISL854102FRZ buck converter; brought out on JANALOG pad 5 and on ICSP pad 2.
+3V3	3.3 V V	SGM2205-3.3XKC3G/TR linear regulator fed from the 5 V rail; it powers the ESP32-S3-MINI-1-N8 and the Qwiic connector, and is brought out on JANALOG pad 4.

Notes

Two headers numbered from 1 by the vendor (JANALOG 1-14, JDIGITAL 1-18), plus JOFF, ICSP and the six-pad ESP header, are folded into this entry's single 1-47 sequence with the connector and the vendor's own pad number named in every description. Every label and description comes from the datasheet's own pin tables (12.1-12.4) and ESP header section, not from a picture; the numbers and the labels were joined by parsing that text, and the ICSP and ESP rows are the vendor's own pad numbering. The ESP header's six pads are included because they are the only way to reach the ESP32-S3's serial port and are 3.3 V. Arduino's digital table contradicts the datasheet's own feature list on the CAN pins (D13/D10 in the table, D4/D5 in the feature list) and labels the D0 pad TX0 while describing it as receive; both are recorded unresolved. The LED matrix occupies eleven internal RA4M1 pins that are not on any header. Arduino sells this board at 30.50 EUR as measured by this campaign's fetcher; the currency is as returned, not converted.

AI context

Dense context for pasting into a model prompt — addresses, pinout, voltages, tolerances and the vendor's reference circuit.

PART: Arduino UNO R4 WiFi, SKU ABX00087, a UNO-form-factor board built around the Renesas R7FA4M1AB3CFM#AA0 (Arm Cortex-M4 with FPU at 48 MHz, 256 kB flash, 32 kB SRAM, 8 kB data flash used as EEPROM, 14-bit ADC, up to 12-bit DAC, on-chip OPAMP, capacitive touch unit, USB 2.0 full-speed, CAN controller). A second MCU, the Espressif ESP32-S3-MINI-1-N8 (Xtensa dual-core LX7, 3.3 V, 40 MHz crystal, 384 kB ROM, 512 kB SRAM, Wi-Fi 4 on 2.4 GHz, Bluetooth 5), supplies the radio and talks to the RA4M1 across a TXB0108DQSR logic-level translator. The board also carries a 12x8 charlieplexed red LED matrix, a Qwiic JST-SH socket, a reset button, a DC jack, a USB-C port, an ICSP header and a six-pad ESP header.
PINOUT: Arduino numbers each header from 1, so no two connectors share a sequence here: JANALOG pads 1-14, JDIGITAL pads 1-18, ICSP pads 1-6, JOFF pads 1-2 plus a VRTC contact and the ESP header J6 pads 1-6. This entry numbers JANALOG 1-14, JDIGITAL 15-32, JOFF 33-35, ICSP J3 36-41 and the ESP header J6 42-47, and every description names its connector and the vendor's own pad number, the same offset convention the Nano R4 entry uses. JANALOG 1-14: BOOT, IOREF, Reset, +3V3, +5V, GND, GND, VIN, A0, A1, A2, A3, A4, A5. JDIGITAL 1-18 in this entry's order (15-32): SCL, SDA, AREF, GND, D13/SCK/CANRX0, D12/CIPO, D11/COPI, D10/CS/CANTX0, D9, D8, D7, D6, D5, D4, D3, D2, D1/TX0, D0. The pinout poster prints the SCL and SDA pads as D19/SCL and D18/SDA, the same nets as A5 and A4.. I2C: two buses and no I2C device on the board, so there are no addresses to record. The main bus is Wire on A4 (SDA) and A5 (SCL), repeated on the digital header as SDA and SCL, at 5 V logic; the secondary bus is I2C0, exposed as Wire1 on the Qwiic connector, at 3.3 V. Arduino states that A4 and A5 must not be used as ADC inputs while the main bus is in use, and that devices may be connected to the analog pads and the digital-header pads at the same time.
SUPPLY: VIN takes 6 V minimum, 7.0 V typical, 24 V maximum from either the VIN pad or the DC jack; the ISL854102FRZ buck converter drops it to 5 V. USB-C takes 4.8-5.5 V and about 4.7 V reaches the MCU after the Schottky drop. VDD - and therefore the logic level - is the 5 V rail; VAREF is the analog reference, brought out on AREF. A SGM2205-3.3XKC3G/TR linear regulator makes the 3.3 V rail that feeds the ESP32-S3 module and the Qwiic connector.
LOGIC LEVEL: every RA4M1 pin is 5 V. The ESP32-S3 side is 3.3 V and is not 5 V tolerant: the full-pinout poster carries two warnings, one on the Qwiic connector (3V3 only, do not connect 5 V parts) and one on the ESP header (do not connect 5 V signals). GPIO current is 8 mA per pin on the RA4M1; the datasheet publishes no board-wide total for this model.
REFERENCE CIRCUIT: the datasheet publishes no I2C pull-up values and no decoupling figures, so none are recorded here. What it does document is the level translation: the RA4M1 and the ESP32-S3 never meet directly, a TXB0108DQSR sits between them, and the two NLASB3157DFT2G multiplexers U2 and U6 switch the USB data path.
TRAPS: (1) The 12x8 LED matrix is charlieplexed onto RA4M1 pins P003, P004, P011, P012, P013, P015, P204, P205, P206, P212 and P213 - internal pins that are not on any header, so a sketch driving the matrix and a sketch using those ports fight. (2) The RA4M1 is programmed through the ESP32-S3 by default; writing a high state to P408 (referred to as D40) hands USB straight to the RA4M1, and soldering the SJ1 pads makes that permanent. (3) CAN is stated twice and inconsistently: the feature list says D4/D5 while the digital pin table gives CAN receive on D13 and CAN transmit on D10; an external transceiver is required either way. (4) The pad labelled D0/TX0 is described by the vendor as 'Serial 0 Receiver (RX)' - label and description disagree. (5) The Qwiic socket is 3.3 V only. (6) The OFF pad controls the board's power supply and VRTC is an RTC backup-battery contact with no ground of its own. (7) Double-tapping reset enters the bootloader if a sketch has locked the board out of USB.

Provenance

Every figure on this page was read from the 5 sources below and last checked on Oct 27, 2026.