m5stack ESP32-S3-PICO-1-N8R8 M5StampS3 BAT Module with Battery Connector

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Dense context for pasting into a model prompt — addresses, pinout, voltages, tolerances and the vendor's reference circuit.

PART: M5Stack Stamp-S3Bat, SKU S015, a 29.8 x 18.0 x 5.5 mm (3.6 g) embedded core module built on the Espressif ESP32-S3-PICO-1-N8R8 - Xtensa LX7 dual-core at 240 MHz, 8 MB flash, 8 MB octal PSRAM, 2.4 GHz Wi-Fi - with an M5Stack M5PM1 (the schematic's PY32 PMIC) doing power-path, charging and rail control. The board adds a USB Type-C port, an SH1.0 3.7 V Li-ion battery connector with an LGS4056HDA charger, a 24-pin BTB connector (supports a DVP camera interface), one WS2812 RGB LED, an IPEX-4 antenna connector and a PWR button.
ADDRESSES: the M5PM1 power-management IC answers at 7-bit I2C address 0x6E, on GPIO47 (SCL) and GPIO48 (SDA) of the ESP32-S3. It is the only device on the board's I2C bus, and both of those pins are also brought out as pins 20 and 24 of the BTB.
PINOUT: the 24-pin BTB (schematic H1) is the connector M5Stack numbers; its table runs odd numbers down the left column and even down the right, pin 1 unpaired: 1 = G40, 2 = G46, 3 = G38, 4 = G45, 5 = G12, 6 = G41, 7 = G13, 8 = U0TX/G43, 9 = G14, 10 = G42, 11 = G15, 12 = G39, 13 = G16, 14 = GND, 15 = G18, 16 = G17, 17 = G21, 18 = U0RX/G44, 19 = 3V3_L2, 20 = SCL, 21 = SYS_VBUS, 22 = GND, 23 = SYS_VBUS, 24 = SDA. The 2.54 mm edge pads are named but never numbered: 11 GPIO (G1-G11) plus one wake input, PY_G4_WAKE, and the power pads 5VIN, 3V3 and VBAT.
SUPPLY: three inputs - a 3.7 V Li-ion cell on the SH1.0 connector, USB Type-C, or DC 5 V - with 5 VIN, 3V3_L2 and VBAT on the 2.54 mm pads. Measured consumption at 4.2 V is 13.43 uA in sleep, 955.36 uA in standby, 26.83 mA light load and 27.49 mA full load. The ESP32-S3 datasheet's absolute maximum on the input power pins is -0.3 to 3.6 V (recommended 3.0-3.3-3.6 V) and its cumulative IO output current limit is 1500 mA. Operating temperature 0 to 40 C.
LOGIC: 3.3 V on every GPIO; the 3V3 rail is regulated by an AP7343D-33FS4 LDO (3V3_L1) and a JW5712 buck (3V3_L2), so 3V3 is an output, not a 5 V logic level. UART0 leaves through R26 (499 ohm 1%) on G43/G44. Anything above 3.6 V on a GPIO exceeds the ESP32-S3's absolute maximum input voltage and can destroy the pin.
REFERENCE CIRCUIT: from the vendor's schematic - the M5PM1's I2C pair carries pull-ups R21 and R23 at 2.2 kOhm 1% to 3V3_L2, so an external I2C device shares an already-pulled-up bus; R24 and R25 on G46/G45 are not fitted (NC). Power path is an AW32901FCR over-voltage protector, four CH213K ideal diodes and an SY7088 boost limited to 0.6 A for the EXT_5V output; charging is an LGS4056HDA (U3) fed from SYS_VIN; USB Type-C uses R1/R2 5.1K CC resistors, 33 ohm R35/R36 series resistors on D-/D+, an SDMM0806H-2-900T common-mode filter and ESD5311 plus LXES15AAA1-153 protection; the ESP32-S3 module is decoupled with C13 100 nF and C14 1 uF, with 4.7 uF (C6) and 100 nF (C5, C16) alongside, and the 3.3 V rails carry 10 uF bulk (C11, C17, C18) plus 100 nF (C19, C31).
TRAPS: (1) M5Stack states that powering the module through the 3V3 interface disables the EXT_5V output - 3V3 in is not a substitute for 5 V in if anything downstream needs the 5 V rail. (2) The housing and the Wi-Fi antenna must be removed before soldering or reflowing the module, or the antenna and housing are damaged. (3) Battery charge current is set by PY_G3_CHG_PROG: low selects 650 mA, floating selects 200 mA - it is not a fixed value. (4) The PWR button is the only power control: one click powers on or resets, a double click powers off, and a long press of about 3 s enters download mode. (5) The 2.54 mm pad rows print GPIO names only; no vendor document numbers them, so a 1-N sequence on those pads is not silkscreen. (6) The vendor contradicts itself on the wake pin's role in the GPIO map table (PY_G4_WAKE is listed both as an external wake input and as a G4 alternate function) - treat it as an input only. (7) SKU S015-DIP is this same PCB with the 2.54 mm headers soldered on.