Verified 2026-10
m5stack M5Stamp LoRa Module (SX1262)
SX1262 LoRa module in stamp form: 12 castellated pads (3.3 V in on 1 and 2, SPI on 8-12, BSY/IRQ/NRST/SWC on 5/4/6/3), 868-923 MHz at +22 dBm for $5.50 USD.
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Part & documents
| Data sheet | Data sheet → |
|---|---|
| Source | shop.m5stack.com/products/m5stamp-lora-module-sx1262 → |
Specs
| MCU | Semtech SX1262 |
|---|
Pinout
12 pads, as the vendor numbers them.
| # | Name | Function | Signals |
|---|---|---|---|
| 1 | VIN_3V3 | Pad 1 - 3.3 V supply in; bridged to pad 2 inside the module. | 3.3 V supply |
| 2 | VIN_3V3 | Pad 2 - 3.3 V supply in; same net as pad 1 on the vendor schematic. | 3.3 V supply |
| 3 | SX_ANT_SW | Pad 3 - RF switch enable (SWC), active high, drives FM8625H U3. | RF switch enable, active high |
| 4 | LORA_IRQ | Pad 4 - interrupt out, SX1262 DIO1 (packet sent/received). | interrupt |
| 5 | SX_BUSY | Pad 5 - busy status; high means the radio is busy, wait for it to fall before a command. | busy status |
| 6 | SX_NRST | Pad 6 - SX1262 reset, active low. | reset |
| 7 | GND | Pad 7 - ground, drawn as a GND symbol on the vendor schematic. | ground |
| 8 | SPI_MISO | Pad 8 - SPI data out of the radio to the host (net SPI_MISO, SX1262 MISO). | SPI MISO |
| 9 | SPI_MOSI | Pad 9 - SPI data in to the radio (net SPI_MOSI, SX1262 MOSI). | SPI MOSI |
| 10 | SX_NSS | Pad 10 - SPI chip select (NSS), active low. | SPI NSS |
| 11 | GND | Pad 11 - ground, drawn as a GND symbol on the vendor schematic. | ground |
| 12 | SPI_CLK | Pad 12 - SPI clock (net SPI_CLK, SX1262 SCK). | SPI clock |
Buses
| Bus | Signals | Pins | Voltage | Note |
|---|---|---|---|---|
| SPI ×1 | SCK, MOSI, MISO, NSS | SPI_CLK, SPI_MOSI, SPI_MISO, SX_NSS |
Power
| Input | 3.3 V on pads 1 and 2 (VIN_3V3) |
|---|---|
| Typical draw | 3.03 mA |
Notes
The vendor publishes no numbered pin table for this module - its Pin Description table lists seven functions with no pad numbers. The 1-12 order above is connector J2's own pad numbering in the vendor's S014_Stamp_LoRa-1262_Sche.pdf: the net labels' y-coordinates run VIN_3V3 (pin 1, and pin 2 tied to it), SX_ANT_SW, LORA_IRQ, SX_BUSY, SX_NRST, two GND symbols, SPI_MISO, SPI_MOSI, SX_NSS and SPI_CLK, which is twelve pads for eleven net names - the double 3V3 accounts for the twelfth. No vision model was needed for the pad labels; one rendered crop was used to confirm which pads the two GND symbols terminate. data sheet is Semtech's SX1261/2 document served from M5Stack's own doc host (application/pdf, 200).
AI context
Dense context for pasting into a model prompt — addresses, pinout, voltages, tolerances and the vendor's reference circuit.
PART: M5Stack Stamp LoRa-1262, SKU S014, a 14.0 x 10.0 x 2.4 mm (0.7 g) stamp-format module built on a Semtech SX1262 LoRa transceiver (U1) with a 3.0 V TCXO (X1, X1G0041310042) and an FM8625H RF switch (U3). The vendor title already carries the silicon, so part is null and the data sheet is Semtech's SX1261/2 document.\nADDRESSES: none. The radio is SPI-only and has no I2C address.\nPINOUT: twelve castellated pads on connector J2, read from the vendor schematic's own J2 symbol and nets, in its pad order: 1 VIN_3V3, 2 VIN_3V3 (pads 1 and 2 are bridged on the module), 3 SX_ANT_SW, 4 LORA_IRQ, 5 SX_BUSY, 6 SX_NRST, 7 GND, 8 SPI_MISO, 9 SPI_MOSI, 10 SX_NSS, 11 GND, 12 SPI_CLK. The vendor's own Pin Description table names the functions as CLK/SCK, NSS, MOSI, MISO, BSY, IRQ and SWC; SWC is drawn as SX_ANT_SW and IRQ as LORA_IRQ (SX1262 DIO1).\nSUPPLY: 3.3 V into pads 1 and 2 only - the module regulates nothing for the host, and its only on-board supply work is the TCXO rail. Published consumption is 3.3 V at 3.03 mA.\nLOGIC: 3.3 V SPI and control; the pads are the SX1262's own I/O, which are not 5 V tolerant - drive NSS, SCK, MOSI and NRST from a 3.3 V source and read MISO/BUSY/IRQ as 3.3 V.\nCIRCUIT: VDD_3V3 enters through FB2, a BLM15AX601SN1D ferrite, with C10 10 uF/10 V, C11 1 uF/10 V, C12 100 nF/25 V, C13 1 uF/10 V, C14 47 nF/25 V and C15/C16 47 pF/25 V on the SX_VREG, SX_PAVDD and PA rails. The TCXO's 3.0 V rail is fed through FB1, a 600 R 0201 ferrite, with C6/C7 100 nF/25 V, C8 10 nF/25 V and C9 10 nF, and R3 220 R/1% in series. The RF switch U3 (FM8625H) sits behind R1/R2 100 R/1% with C4/C5 100 pF/25 V, and the antenna port carries a 39 pF high-Q capacitor and L1 LQW15AN47NJ00D 47 nH with L4 0 R/TBD. No I2C pull-ups exist because there is no I2C bus.\nTRAPS: (1) BSY is high while the radio is busy and every command must wait for it to fall - the vendor states it explicitly. (2) SWC (pad 3) is the RF switch enable and is active high, so a receiver that never raises it hears nothing. (3) Only the S014-I adds the IPEX-4 antenna connector and only the S014-IF adds both the IPEX-4 and the 0.5 mm 12-pin FPC connector, so on plain S014 the only way in is the castellated pads and a wire antenna. (4) There is no regulator and no level shifting on the module.
Provenance
Every figure on this page was read from the 4 sources below and last checked on Oct 31, 2026.
- product M5Stack store product page (price 5.50 USD as measured, S014-I/S014-IF variants)
- reference M5Stack docs - Stamp LoRa-1262 (specification, 7-function Pin Description, variant table)
- reference Schematic S014_Stamp_LoRa-1262_Sche (J2 pads 1-12 and their nets, TCXO/ferrite/decoupling values, FM8625H)
- datasheet Semtech SX1261/SX1262 data sheet DS_SX1261-2 Rev 2.2 (served from M5Stack's doc host)