Verified 2026-11
m5stack M5Stamp UWB Module (QM33120W)
QM33120W UWB ranging module in stamp form: 12 pads (3.3 V on pad 2, SPI on 7/9/10/11, WAKEUP/IRQ/RSTn on 3/4/6), Channel 9 at 7987.2 MHz, 55 m range, $23.50 USD.
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Part & documents
| Data sheet | Data sheet → |
|---|---|
| Source | shop.m5stack.com/products/m5stamp-uwb-module-qm33120w → |
Specs
| MCU | Qorvo QM33120W |
|---|
Pinout
12 pads, as the vendor numbers them.
| # | Name | Function | Signals |
|---|---|---|---|
| 1 | GND | Pad 1 - ground. | ground |
| 2 | VCC_3V3 | Pad 2 - 3.3 V supply in; the module's only supply pad. | 3.3 V supply |
| 3 | DW_WAKEUP | Pad 3 - WAKEUP input to the QM33120W, with R1 10 kOhm/1% on the net. | wake input |
| 4 | DW_IRQ | Pad 4 - interrupt out, chip pin IRQ/GPIO9, pulled up by R2 10 kOhm/1% to VCC_3V3. | interrupt |
| 5 | DW_GP7 | Pad 5 - chip pin GPIO7/SYNC, the one general-purpose GPIO broken out. | GPIO, sync |
| 6 | DW_RSTn | Pad 6 - active-low reset to the QM33120W (chip pin RSTn). | reset, active low |
| 7 | DW_CDO | Pad 7 - SPI data out from the radio (SPICDO), i.e. MISO to the host. | SPI MISO |
| 8 | GND | Pad 8 - ground. | ground |
| 9 | DW_CDI | Pad 9 - SPI data in to the radio (SPICDI), i.e. MOSI from the host. | SPI MOSI |
| 10 | DW_CSn | Pad 10 - active-low SPI chip select (SPICSn). | SPI CS, active low |
| 11 | DW_CLK | Pad 11 - SPI clock (SPICLK). | SPI clock |
| 12 | GND | Pad 12 - ground; same end of the module as pad 1, so the two rows run in opposite directions. | ground |
Buses
| Bus | Signals | Pins | Voltage | Note |
|---|---|---|---|---|
| SPI ×1 | CLK, MOSI, MISO, CS | DW_CLK, DW_CDI, DW_CDO, DW_CSn |
Power
| Input | 3.3 V on pad 2 (VCC_3V3) |
|---|---|
| Typical draw | 5.23 mA |
Notes
The vendor's docs page has a 'PinMap' heading with no table under it, so the pad numbers and labels come from the PINMAP graphic printed inside the vendor's own schematic (SCH_UWB_MODULE_SCH_main_V0.2), where pads 1-6 run down one column and 12-7 down the other - the row order reverses at pad 7. The S017-F variant is the same PCB with the 0.5 mm-12P FPC connector soldered and a cable in the box, so it is not a separate entry. The vendor asks for supply ripple within 12 mVpp, which is tighter than a typical dev-board regulator's spec.
AI context
Dense context for pasting into a model prompt — addresses, pinout, voltages, tolerances and the vendor's reference circuit.
PART: M5Stack Stamp UWB, SKU S017, an 11.5 x 12.0 x 1.6 mm (0.5 g) stamp-format module built on a Qorvo QM33120W UWB transceiver (U1, marked QM33120WTR13) with a 38.4 MHz TCXO (X1, SX0B38.400F0810F30) and an on-board JW5712 buck-boost (U2) making the chip's 1.8 V rail. The vendor title already carries the silicon, so part is null and the data sheet is Qorvo's QM33120W document. 1.27 mm castellated pads for SMT mounting. ADDRESSES: none. The radio is SPI-only and has no I2C address. PINOUT: twelve pads on connector J1, in the vendor schematic's own numbered PinMap graphic: 1 GND, 2 VCC_3V3, 3 DW_WAKEUP, 4 DW_IRQ (chip pin IRQ/GPIO9), 5 DW_GP7 (chip pin GPIO7/SYNC), 6 DW_RSTn, 7 DW_CDO (SPICDO), 8 GND, 9 DW_CDI (SPICDI), 10 DW_CSn, 11 DW_CLK (SPICLK), 12 GND. The graphic prints pads 1-6 down the left column and 12-7 down the right, so the two rows run in opposite directions - pad 12 and pad 1 are at the same end. SUPPLY: 3.3 V on pad 2 only. Published figures: 75.9 uA asleep at 3.3 V, 5.23 mA as a base station, 58.0 mA as a slave. The vendor requires a high-PSRR LDO or a supply with ripple within 12 mVpp. LOGIC: 3.3 V SPI and control, direct to the QM33120W's own I/O; nothing on the module is 5 V tolerant and there is no level shifting fitted. CIRCUIT: VCC_3V3 arrives on pad 2 with C1 1 nF/50 V at the pin, C6 10 uF/10 V and C2 10 uF/10 V on the VCC_3V3 rail, and U2 (JW5712) plus L1 (FTC121065S2R2MBCA, 2.2 uH) and C3 10 uF/10 V generating VCC_1V8; the 1.8 V rail carries C8 100 nF/25 V. The RF front end runs DW_RF1/DW_RF2 through C12 and C5 (GJM1555C1H2R0B, 2.0 pF) with C4/C9/C10 4.7 nF/50 V and C16 100 nF/25 V / C17 220 nF/25 V on the supply pins; FB1 is a 600 R @ 100 MHz ferrite into VCCA_3V3 with C13 100 nF/25 V and C14 100 nF/25 V. R1 is 10 kOhm/1% on DW_WAKEUP and R2 is 10 kOhm/1% on DW_IRQ (its net is VCC_3V3), so wake and interrupt can be left open-drain by the host. The TCXO has C18/C19 3.3 pF. TRAPS: (1) The vendor warns that this module's FPC pad pinout is NOT compatible with the FPC pinout on the back of the Stamp-S3/S3A - wiring it to one can permanently damage the device. (2) The antenna area must hang completely off the edge of any baseboard with no copper pour, trace, component or metal beneath or around it, or ranging accuracy degrades. (3) Only the S017-F version has the 0.5 mm-12P FPC connector soldered and the cable included; on plain S017 the castellated pads are the only connection. (4) There is no regulator for the host supply on the module - 3.3 V in, nothing regulated out.
Provenance
Every figure on this page was read from the 4 sources below and last checked on Nov 2, 2026.
- product M5Stack Stamp UWB product page (S017)
- documentation M5Stack docs - Stamp UWB, PinMap and specifications
- schematic M5Stack Stamp UWB schematic (numbered J1 PinMap graphic)
- datasheet Qorvo QM33120W data sheet