pimoroni M.2 HAT+

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Dense context for pasting into a model prompt — addresses, pinout, voltages, tolerances and the vendor's reference circuit.

BOARD: the Raspberry Pi M.2 HAT+ is an adapter board that converts the single-lane PCIe 2.0 connector on Raspberry Pi 5 into one M.2 M-key socket, taking 2230 and 2242 modules. Pimoroni's page quotes up to 500 MB/s peak transfer and says the board can supply up to 3 A to the M.2 device, recommending the official PSU; the board conforms to the HAT+ specification and is autodetected by current Raspberry Pi firmware. It ships with a 16 mm stacking header, the PCIe ribbon cable, threaded spacers and a knurled double-flanged drive screw. The Compact variant is the same adapter for 2230 modules only, and fits inside the official Raspberry Pi 5 case.
CONNECTORS: three of them, and only one is a numbered pin list in the schematic: J3, the M.2 M-key socket (MTSSD03-67MSW337), whose 69 pads are listed in `pins` using the socket's own M.2 numbering - pads 1 to 58 and 67 to 77, the gap being the M-key notch. J1 is a 2x20 (HLE-120-02-F-DV-BE-A) 40-pin stacking header that carries the Pi's GPIO through, with ID_SD on pad 27 and ID_SC on pad 28 wired to the EEPROM. J2 is the 16-pin PCIe ribbon connector (1-1734839-6) plus shield pads, carrying PCIE_TX_P/N, PCIE_RX_P/N, PCIE_CLK_P/N, PCIE_CLKREQ_N, PCIE_RST_B and PCIE_PEWAKE_N.
SOCKET PIN MAP: SUPPLY: 5 V arrives over the stacking header and is regulated down to the socket's 3.3 V rail (3V3_M2) by an AP3441SHE-7B buck converter, U1, with a 2u2 inductor (L1) and 10 uF 25 V X7R ceramics on input and output (C7, C10, C2, C5, C6, C8) plus 100 nF (C1, C9) for high-frequency decoupling. The socket's own 3V3 pads are 2, 4, 12, 14, 16, 18, 70, 72 and 74; its grounds are 1, 3, 9, 15, 21, 27, 33, 39, 45, 51, 57, 71 and 73, and the shield pads 76 and 77.
LOGIC LEVEL AND TOLERANCES: the PCIe pairs are differential and need no level shifting, but the socket's SMBus side is 1.8 V, not 3.3 V - the schematic names those nets SMB_CLK_1V8, SMB_DAT_1V8 and ALERT_N_1V8, so anything hanging off pads 40, 42 and 44 must be 1.8 V logic. PEDET (pad 69) identifies the module type to the host.
REFERENCE CIRCUIT: everything an M.2 device needs is already fitted - the buck converter and its ceramics, a 32.768 kHz oscillator (X1) for the socket's SUSCLK with the schematic annotating 3.5 mA maximum oscillator current, a PEWAKE pull-up inside the range the schematic notes from the PCIe spec (9 k to 60 k), and the HAT+ ID EEPROM U2 (M24C32-FMN6TP) on the ID_SD/ID_SC pair. Two DMG1012T MOSFETs and an NC7SB3157P6X analogue switch sit on CLKREQ and RESET, annotated 'belt and braces isolate CLKREQ and RESET when M2 power off'; the switch is strapped SEL 1 = B1, 0 = B0.
TRAPS: it is an M-key socket, so B-key and A/E-key modules do not fit. PEDET is shorted to ground on a SATA module and left open on a PCIe module, so a SATA M.2 device is identified as SATA and will not appear on PCIe. DEVSLP (pad 38) is a SATA-module signal and is not used for PCIe. The schematic notes that the positive and negative members of the TX and RX pairs are swapped for better routing - that is a polarity swap on the PCB, not an error to be unwound. 3 A for the SSD depends on a supply that can give it, hence the official-PSU recommendation. Autodetection depends on the HAT+ EEPROM, so stale firmware will not see the board. The 40-pin header and the PCIe ribbon are not in `pins` because the schematic numbers them but publishes no net-per-pad list in its text layer; they are described here instead of being guessed.
ADDRESSES: the HAT+ EEPROM is an M24C32 whose A0/A1/A2 straps are not shown in the schematic text, so no I2C address is recorded.