Verified 2026-10

pimoroni RP2350B Pico LiPo 2 XL W

Pico-shaped but 24 mm longer RP2350B board (dual Cortex-M33 or Hazard3 at 150 MHz, 520 kB SRAM, 16 MB flash, 8 MB PSRAM) with an RM2 wireless module, LiPo charging and protection, USB-C, Qw/ST and SP/CE, and two 30-pin rows of 3.3 V GPIO - $20.00 USD as measured.

Place this board on a carrier in the editor →

Logic level3.3 V

Part & documents

Headline part	RP2350B
Data sheet	RP2350B data sheet →
Source	shop.pimoroni.com/products/pimoroni-pico-lipo-2-xl-w →

Specs

MCU	Raspberry Pi RP2350B (dual Arm Cortex-M33 at up to 150 MHz, 520 kB SRAM, 48 GPIO, 8 ADC, 24 PWM) plus a Raspberry Pi RM2 wireless module
Clock	150 MHz
RAM	520 KB

Pinout

60 pads, as the vendor numbers them.

#	Name	Function	Signals
1	0	Pad 1 (left column, pad 1 of 30 counted from the USB-C end): printed 0 - 3.3 V GP0 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP0
2	1	Pad 2 (left column, pad 2 of 30 counted from the USB-C end): printed 1 - 3.3 V GP1 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP1
3	GND	Pad 3 (left column, pad 3 of 30 counted from the USB-C end): GND, ground.	ground
4	2	Pad 4 (left column, pad 4 of 30 counted from the USB-C end): printed 2 - 3.3 V GP2 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP2
5	3	Pad 5 (left column, pad 5 of 30 counted from the USB-C end): printed 3 - 3.3 V GP3 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP3
6	4	Pad 6 (left column, pad 6 of 30 counted from the USB-C end): printed 4 - 3.3 V GP4 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. The Qw/ST socket's SDA pin is on this net (GP4_SDA).	GP4
7	5	Pad 7 (left column, pad 7 of 30 counted from the USB-C end): printed 5 - 3.3 V GP5 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. The Qw/ST socket's SCL pin is on this net (GP5_SCL).	GP5
8	GND	Pad 8 (left column, pad 8 of 30 counted from the USB-C end): GND, ground.	ground
9	6	Pad 9 (left column, pad 9 of 30 counted from the USB-C end): printed 6 - 3.3 V GP6 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP6
10	7	Pad 10 (left column, pad 10 of 30 counted from the USB-C end): printed 7 - 3.3 V GP7 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP7
11	8	Pad 11 (left column, pad 11 of 30 counted from the USB-C end): printed 8 - 3.3 V GP8 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP8
12	9	Pad 12 (left column, pad 12 of 30 counted from the USB-C end): printed 9 - 3.3 V GP9 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP9
13	GND	Pad 13 (left column, pad 13 of 30 counted from the USB-C end): GND, ground.	ground
14	10	Pad 14 (left column, pad 14 of 30 counted from the USB-C end): printed 10 - 3.3 V GP10 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP10
15	11	Pad 15 (left column, pad 15 of 30 counted from the USB-C end): printed 11 - 3.3 V GP11 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP11
16	12	Pad 16 (left column, pad 16 of 30 counted from the USB-C end): printed 12 - 3.3 V GP12 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. HSTX-capable.	GP12
17	13	Pad 17 (left column, pad 17 of 30 counted from the USB-C end): printed 13 - 3.3 V GP13 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. HSTX-capable.	GP13
18	GND	Pad 18 (left column, pad 18 of 30 counted from the USB-C end): GND, ground.	ground
19	14	Pad 19 (left column, pad 19 of 30 counted from the USB-C end): printed 14 - 3.3 V GP14 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. HSTX-capable.	GP14
20	15	Pad 20 (left column, pad 20 of 30 counted from the USB-C end): printed 15 - 3.3 V GP15 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. HSTX-capable.	GP15
21	3V3	Pad 21 (left column, pad 21 of 30 counted from the USB-C end): 3V3, the regulator's 3.3 V output; the board's 600 mA regulator budget covers this pad too.	3.3 V output of the on-board regulator
22	31	Pad 22 (left column, pad 22 of 30 counted from the USB-C end): printed 31 - 3.3 V GP31 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. This is the first GPIO past the 3V3 pad; the SP/CE connector's lines start here.	GP31
23	GND	Pad 23 (left column, pad 23 of 30 counted from the USB-C end): GND, ground.	ground
24	32	Pad 24 (left column, pad 24 of 30 counted from the USB-C end): printed 32 - 3.3 V GP32 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP32
25	33	Pad 25 (left column, pad 25 of 30 counted from the USB-C end): printed 33 - 3.3 V GP33 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP33
26	34	Pad 26 (left column, pad 26 of 30 counted from the USB-C end): printed 34 - 3.3 V GP34 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP34
27	35	Pad 27 (left column, pad 27 of 30 counted from the USB-C end): printed 35 - 3.3 V GP35 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP35
28	GND	Pad 28 (left column, pad 28 of 30 counted from the USB-C end): GND, ground.	ground
29	36	Pad 29 (left column, pad 29 of 30 counted from the USB-C end): printed 36 - 3.3 V GP36 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP36
30	37	Pad 30 (left column, pad 30 of 30 counted from the USB-C end): printed 37 - 3.3 V GP37 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP37
31	38	Pad 31 (right column, pad 30 of 30 counted from the USB-C end): printed 38 - 3.3 V GP38 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP38
32	39	Pad 32 (right column, pad 29 of 30 counted from the USB-C end): printed 39 - 3.3 V GP39 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP39
33	GND	Pad 33 (right column, pad 28 of 30 counted from the USB-C end): GND, ground.	ground
34	43/A3	Pad 34 (right column, pad 27 of 30 counted from the USB-C end): printed 43/A3 - 3.3 V GP43 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP43, ADC3, VBAT sense - cut the 'BtS Cut' trace to free the pin
35	44/A4	Pad 35 (right column, pad 26 of 30 counted from the USB-C end): printed 44/A4 - 3.3 V GP44 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP44
36	45/A5	Pad 36 (right column, pad 25 of 30 counted from the USB-C end): printed 45/A5 - 3.3 V GP45 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP45
37	46/A6	Pad 37 (right column, pad 24 of 30 counted from the USB-C end): printed 46/A6 - 3.3 V GP46 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP46
38	GND	Pad 38 (right column, pad 23 of 30 counted from the USB-C end): GND, ground.	ground
39	47/A7	Pad 39 (right column, pad 22 of 30 counted from the USB-C end): printed 47/A7 - 3.3 V GP47 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP47, ADC7, PSRAM chip select - cut the 'PSRAM Cut' trace to free the pin
40	BOOT	Pad 40 (right column, pad 21 of 30 counted from the USB-C end): printed BOOT - GP30, the pin the BOOT/user button pulls to ground (active low); also broken out here so an external switch can do the same.	GP30, BOOT/user button, active low
41	16	Pad 41 (right column, pad 20 of 30 counted from the USB-C end): printed 16 - 3.3 V GP16 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. HSTX-capable.	GP16
42	17	Pad 42 (right column, pad 19 of 30 counted from the USB-C end): printed 17 - 3.3 V GP17 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. HSTX-capable.	GP17
43	GND	Pad 43 (right column, pad 18 of 30 counted from the USB-C end): GND, ground.	ground
44	18	Pad 44 (right column, pad 17 of 30 counted from the USB-C end): printed 18 - 3.3 V GP18 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. HSTX-capable.	GP18
45	19	Pad 45 (right column, pad 16 of 30 counted from the USB-C end): printed 19 - 3.3 V GP19 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster. HSTX-capable.	GP19
46	20	Pad 46 (right column, pad 15 of 30 counted from the USB-C end): printed 20 - 3.3 V GP20 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP20
47	21	Pad 47 (right column, pad 14 of 30 counted from the USB-C end): printed 21 - 3.3 V GP21 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP21
48	GND	Pad 48 (right column, pad 13 of 30 counted from the USB-C end): GND, ground.	ground
49	22	Pad 49 (right column, pad 12 of 30 counted from the USB-C end): printed 22 - 3.3 V GP22 of the RP2350B, muxable to the SPI/I2C/UART/PWM functions printed on the poster.	GP22
50	RUN	Pad 50 (right column, pad 11 of 30 counted from the USB-C end): RUN, active low reset.	active low reset
51	26/A0	Pad 51 (right column, pad 10 of 30 counted from the USB-C end): printed 26/A0 - digital GP26 straight off the header, and the analogue channel ADC0 (chip GPIO40) reaches the RP2350B's ADC through a 1 kOhm element of the RN2 network.	GP26
52	27/A1	Pad 52 (right column, pad 9 of 30 counted from the USB-C end): printed 27/A1 - digital GP27 straight off the header, and the analogue channel ADC1 (chip GPIO41) reaches the RP2350B's ADC through a 1 kOhm element of the RN2 network.	GP27
53	GND	Pad 53 (right column, pad 8 of 30 counted from the USB-C end): GND, ground.	ground
54	28/A2	Pad 54 (right column, pad 7 of 30 counted from the USB-C end): printed 28/A2 - digital GP28 straight off the header, and the analogue channel ADC2 (chip GPIO42) reaches the RP2350B's ADC through a 1 kOhm element of the RN2 network.	GP28
55	ADC_VREF	Pad 55 (right column, pad 6 of 30 counted from the USB-C end): ADC_VREF, analogue reference input.	analogue reference input
56	3V3	Pad 56 (right column, pad 5 of 30 counted from the USB-C end): 3V3, the regulator's 3.3 V output; the board's 600 mA regulator budget covers this pad too.	3.3 V output of the on-board regulator
57	3V3 EN	Pad 57 (right column, pad 4 of 30 counted from the USB-C end): 3V3 EN, the regulator enable driven by the board's power latch - not a free GPIO.	3.3 V regulator enable (driven by the board's power latch)
58	GND	Pad 58 (right column, pad 3 of 30 counted from the USB-C end): GND, ground.	ground
59	VSYS	Pad 59 (right column, pad 2 of 30 counted from the USB-C end): VSYS, the rail behind the 3.3 V regulator - USB input is rated 3 V to 5.5 V and the LiPo feeds the same node.	system rail behind the regulator
60	VBUS	Pad 60 (right column, pad 1 of 30 counted from the USB-C end): VBUS, USB 5 V; on this board the USB-present sense is taken to the wireless module, not to a GPIO.	USB 5 V rail

Buses

Bus	Signals	Pins	Voltage	Note
I2C ×2	SDA, SCL	GP4 (Qw/ST SDA), GP5 (Qw/ST SCL)	3.3 V V	Qw/ST 4-pin JST-SH on I2C0 as GP4_SDA / GP5_SCL; the schematic fits no pull-ups on those nets.
SPI ×2	CS, SCK, TX/MOSI, RX/MISO, BL	GP33, GP34, GP35, GP32, GP36	3.3 V V	8-pin SP/CE socket printed VSYS, 3V3, CS, SCK, TX, RX, BL, GND; the schematic names its nets GP32/UART_TX/DC to GP36/PWRKEY/BL.
UART ×2	TX, RX	GP32, GP33	3.3 V V	UART on the SP/CE socket (schematic nets GP32/UART_TX/DC, GP33/UART_RX/CS).
SWD ×1	SWCLK, SWDIO	SWCLK, SWDIO	3.3 V V	3-pin JST-SH debug socket, printed SWCLK, GND, SWDIO.

Power

Input	3-5.5 V on the USB-C input, or a 3.7 V single-cell LiPo/Li-Ion on the JST-PH battery socket
Input range	USB 3-5.5 V; LiPo 3.7 V cell

Outputs

Rail	Rating	Note
3V3	3.3 V V	on-board regulator rated 600 mA maximum output, brought out on pads 21 and 56

Notes

Pimoroni prints GPIO numbers on the silkscreen, not pad numbers, so the 1-60 numbering is the Pico header convention extended to two 30-pin rows - 1-30 down the left edge from the USB end, 60-31 down the right - and the schematic's own symbol nets run in exactly this order. Every pad's description names its column and printed label. Labels were read from the pinout PDF's text layer (unlike the Pico LiPo 2 and Plus 2 W posters, this one carries its pad labels as text), with the peripheral columns taken from the same file. Pimoroni's page says '40 exposed GPIO' over two 30-pin rows; counting the printed header labels gives 41 GPIO pads because GP30 (the BOOT button) is also broken out. Both figures are recorded here as published - the pad labels are what the header actually prints. The analogue pads print 26/A0, 27/A1, 28/A2 but reach ADC0-2 on chip GPIO40-42 through RN2 1 kOhm elements; GP43 and GP47 are wired to battery sense and PSRAM select and need their cut traces severed to be used. The SP/CE connector's per-pin GPIO join is not printed as a table, so the nets the schematic names (GP32-GP36) are recorded rather than a pin-by-pin guess. Pimoroni states current stock is RP2350 stepping A4, so the RP2350-E9 erratum noted on the Pico LiPo 2 does not apply to the stock as described. Charger passives on this board's schematic are not in its text layer, so only the parts and the vendor's stated 215 mA are recorded.

AI context

Dense context for pasting into a model prompt — addresses, pinout, voltages, tolerances and the vendor's reference circuit.

PART: Pimoroni Pico LiPo 2 XL W, order code PIM776, a 77 x 21 mm (about 77 x 21 x 10 mm including connectors, 76.4 mm board length) board 24 mm longer than a Pico, built on the RP2350B: dual Arm Cortex-M33 at up to 150 MHz, 520 kB SRAM, 48 usable GPIO, 8 ADC channels, 24 PWM channels, with optional RISC-V Hazard3 cores instead of the M33s. Around it: 16 MB QSPI flash (XiP), 8 MB PSRAM, a Raspberry Pi RM2 module for 2.4 GHz wireless and Bluetooth, an MCP73831 single-cell LiPo charger set for 215 mA, an XB6096I2S battery protector, a 3.3 V regulator rated 600 mA, USB-C, a Qw/ST (Qwiic/STEMMA QT) I2C socket, an 8-pin SP/CE socket, a 3-pin JST-SH debug socket, reset/BOOT buttons, a power button and a JST-PH battery socket. Pimoroni states current stock is RP2350 stepping A4.
ADDRESSES: none. Nothing on the board answers I2C; a bus scan sees only what is plugged into Qw/ST.
PINOUT: two rows of 30 pins, 2.54 mm, printed GPIO numbers only (no pad numbers). Numbering here is the Pico convention extended to 60: 1-30 down the left edge from the USB-C end, 60-31 down the right edge, so pad 1 (GP0) and pad 60 (VBUS) share the USB end. LEFT, pads 1-30: 1=0, 2=1, 3=GND, 4=2, 5=3, 6=4, 7=5, 8=GND, 9=6, 10=7, 11=8, 12=9, 13=GND, 14=10, 15=11, 16=12, 17=13, 18=GND, 19=14, 20=15, 21=3V3, 22=31, 23=GND, 24=32, 25=33, 26=34, 27=35, 28=GND, 29=36, 30=37. RIGHT, pads 31-60 from the far end back to USB: 31=38, 32=39, 33=GND, 34=43/A3, 35=44/A4, 36=45/A5, 37=46/A6, 38=GND, 39=47/A7, 40=BOOT, 41=16, 42=17, 43=GND, 44=18, 45=19, 46=20, 47=21, 48=GND, 49=22, 50=RUN, 51=26/A0, 52=27/A1, 53=GND, 54=28/A2, 55=ADC_VREF, 56=3V3, 57=3V3 EN, 58=GND, 59=VSYS, 60=VBUS. Twelve of the 60 pads are GND and there are two 3V3 pads, one per row. Not on the header: GP23/24/25/29 are the RM2 link (WL_ON/WL_D/WL_CS/WL_CLK), the user LED is the module's WL_GPIO0, USB presence is the module's WL_GPIO2. Qw/ST is I2C0 with SDA on GP4 and SCL on GP5; the SP/CE socket prints VSYS, 3V3, CS, SCK, TX, RX, BL, GND and its lines are GP32-GP36 (schematic nets GP32/UART_TX/DC through GP36/PWRKEY/BL).
SUPPLY: USB-C input rated 3 V to 5.5 V, or a 3.7 V single-cell LiPo/Li-Ion on the JST-PH socket (polarity printed on the board). The on-board 3.3 V regulator is rated 600 mA maximum. 3V3 EN is driven by the board's own power latch, so it is not a free GPIO.
LOGIC LEVEL: 3.3 V everywhere; the RP2350B I/O is not 5 V tolerant and a 5 V source needs level shifting.
ANALOGUE: the analogue pads print 26/A0, 27/A1, 28/A2 (ADC channels 0-2 on chip GPIO40-42) and 43/A3, 44/A4, 45/A5, 46/A6, 47/A7 (ADC3-7). The three A0-A2 pads reach their ADC pins through 1 kOhm elements of RN2, which the poster annotates as an internal 1 kOhm - count it as source impedance. Two analogue-capable pins are spoken for on the board: GP43 senses battery voltage and GP47 is the PSRAM chip select, so using either as an input means cutting the trace marked 'BtS Cut' or 'PSRAM Cut' on the underside.
REFERENCE CIRCUIT: MCP73831 charger at 215 mA with the XB6096I2S protector in series with the battery (bypassable for more than 800 mA by soldering the '+1A Mode' trace, only with a cell that can deliver it), a power latch driven by the 74LVC1G74 flip-flop, the RN2 1 kOhm array on the A0-A2 pins, and the RM2 module on WL_ON/WL_D/WL_CS/WL_CLK. Pimoroni publishes no pull-up resistors on the Qw/ST SDA and SCL nets, so an I2C add-on must bring its own.
TRAPS: (1) This is not a 40-pin Pico footprint - add-ons must be fitted towards the USB end, and the extra column of pins is not Pico-wired. (2) GP43 and GP47 are wired to battery sense and PSRAM select unless their cut traces are severed. (3) GP30 is the BOOT button and is exposed on the right-hand header, so an external pull to ground there reboots into the bootloader. (4) The user LED and USB-present sense are inside the RM2 module (WL_GPIO0, WL_GPIO2) and cannot be read as main-bank GPIO. (5) LiPo/Li-Ion cells only - the MCP73831 is set for a 3.7 V single cell. (6) Headers, battery and cables are not included.

Provenance

Every figure on this page was read from the 6 sources below and last checked on Oct 26, 2026.