sparkfun ATmega328P RedBoard Plus — pinout, specs

Part & documents

Headline part	ATmega328P
Data sheet	ATmega328P data sheet →
Source	www.sparkfun.com/sparkfun-redboard-plus.html →

Specs

MCU	Microchip ATmega328P (8-bit AVR, 16 MHz, 32 kB flash, 1 kB EEPROM, 2 kB SRAM) with the Optiboot UNO bootloader
Clock	16 MHz
Flash	0.03125 MB
RAM	2 KB
I/O	22 digital, 8 analog, 6 PWM

SparkFun's own count: 22 digital I/O with 6 PWM outputs, 8 analog inputs, one UART, one I2C and one SPI. The 8 analog inputs are A0-A7, and A4/A5 double as SDA/SCL. A6 and A7 are analog-only - they have no digital driver stage. PWM is 8-bit and the ADC is 10-bit.

Pinout

44 pads, as the vendor numbers them.

#	Name	Function	Signals
1	VIN	Power header pad 1: VIN, 7-15 V from the barrel jack into the LM1117 regulator	supply in, feeds LM1117 5 V regulator
2	GND	Power header pad 2: GND	ground
3	GND	Power header pad 3: GND	ground
4	5V	Power header pad 4: 5 V, the LM1117 regulator's output and the ATmega328P's supply	5 V rail, LM1117 output
5	3.3V	Power header pad 5: 3.3 V, the AP2112 regulator's output, up to 600 mA for Qwiic devices	3.3 V rail, AP2112 output
6	RESET	Power header pad 6: RESET (fab net !RESET), active low, same net as the reset button and the ISP header's pin 5	reset, active low
7	IOREF	Power header pad 7: IOREF (fab net VCC), the I/O reference rail - its voltage is whatever the Red Squirrel I/O switch selects, 5 V or 3.3 V	I/O reference
8	NC	Power header pad 8: no net in the fab file - the graphical datasheet marks it NC	not connected
9	A0	Analog header pad 1: A0, ATmega328P PC0, ADC0, PCINT8, also D14	analog in, ATmega328P PC0, digital I/O
10	A1	Analog header pad 2: A1, ATmega328P PC1, ADC1, PCINT9, also D15	analog in, ATmega328P PC1, digital I/O
11	A2	Analog header pad 3: A2, ATmega328P PC2, ADC2, PCINT10, also D16	analog in, ATmega328P PC2, digital I/O
12	A3	Analog header pad 4: A3, ATmega328P PC3, ADC3, PCINT11, also D17	analog in, ATmega328P PC3, digital I/O
13	A4/SDA	Analog header pad 5: A4, which is also SDA (PC4, ADC4, PCINT12, also D18). Passes through the on-board logic level converter to the Qwiic connector unless jumper QW1 is cut	analog in, I2C SDA, ATmega328P PC4
14	A5/SCL	Analog header pad 6: A5, which is also SCL (PC5, ADC5, PCINT13, also D19). Passes through the on-board logic level converter to the Qwiic connector unless jumper QW2 is cut	analog in, I2C SCL, ATmega328P PC5
15	RX<-0	Digital header pad 1 (D0): ATmega328P PD0, RXD, PCINT16 - the CH340G's TX lands here	digital I/O, ATmega328P PD0
16	TX->1	Digital header pad 2 (D1): ATmega328P PD1, TXD, PCINT17 - the CH340G's RX lands here	digital I/O, ATmega328P PD1
17	D2	Digital header pad 3 (D2): ATmega328P PD2, INT0, PCINT18	digital I/O, ATmega328P PD2
18	D3	Digital header pad 4 (D3): ATmega328P PD3, INT1, PCINT19, OC2B (PWM)	digital I/O, ATmega328P PD3
19	D4	Digital header pad 5 (D4): ATmega328P PD4, T0, PCINT20, XCK	digital I/O, ATmega328P PD4
20	D5	Digital header pad 6 (D5): ATmega328P PD5, T1, PCINT21, OC0B (PWM)	digital I/O, ATmega328P PD5
21	D6	Digital header pad 7 (D6): ATmega328P PD6, AIN0, PCINT22, OC0A (PWM)	digital I/O, ATmega328P PD6
22	D7	Digital header pad 8 (D7): ATmega328P PD7, IN1, PCINT23	digital I/O, ATmega328P PD7
23	SCL	Digital header pad 1A: SCL/SDA pair position - SCL, ATmega328P PC5, A5/D19, ADC5, PCINT13 - the same net as analog pad 6	I2C SCL, ATmega328P PC5
24	SDA	Digital header pad 2A: SCL/SDA pair position - SDA, ATmega328P PC4, A4/D18, ADC4, PCINT12 - the same net as analog pad 5	I2C SDA, ATmega328P PC4
25	AREF	Digital header pad 3A: AREF, the ADC's external reference pin	ADC reference
26	GND	Digital header pad 4A: GND	ground
27	D13	Digital header pad 5A: D13, ATmega328P PB5, SCK, PCINT5 - drives the blue pin-13 LED	digital I/O, ATmega328P PB5
28	D12	Digital header pad 6A: D12, ATmega328P PB4, CIPO (MISO), PCINT4	digital I/O, ATmega328P PB4
29	D11	Digital header pad 7A: D11, ATmega328P PB3, COPI (MOSI), PCINT3, OC2A (PWM)	digital I/O, ATmega328P PB3
30	D10	Digital header pad 8A: D10, ATmega328P PB2, CS, PCINT2, OC1B (PWM)	digital I/O, ATmega328P PB2
31	D9	Digital header pad 9A: D9, ATmega328P PB1, PCINT1, OC1A (PWM)	digital I/O, ATmega328P PB1
32	D8	Digital header pad 10A: D8, ATmega328P PB0, PCINT0, ICP1, CLKO	digital I/O, ATmega328P PB0
33	A6	J1 pad 1: A6, ADC6 - analog input only, no digital driver stage and no internal pull-up on this pin	analog in only, ATmega328P ADC6
34	A7	J1 pad 2: A7, ADC7 - analog input only, like A6	analog in only, ATmega328P ADC7
35	CIPO	2x3 ISP header pad 1: CIPO (MISO)	ISP programming
36	VCC	2x3 ISP header pad 2: VCC - the I/O reference rail, i.e. 5 V or 3.3 V depending on the switch	ISP programming
37	SCK	2x3 ISP header pad 3: SCK	ISP programming
38	COPI	2x3 ISP header pad 4: COPI (MOSI)	ISP programming
39	RESET	2x3 ISP header pad 5: RESET, active low, shared with the reset button	ISP programming
40	GND	2x3 ISP header pad 6: GND	ISP programming
41	GND	Qwiic (1 mm JST-SH) pad 1: GND	Qwiic I2C
42	3.3V	Qwiic (1 mm JST-SH) pad 2: 3.3 V from the AP2112 regulator	Qwiic I2C
43	SDA	Qwiic (1 mm JST-SH) pad 3: SDA through the logic level converter (fab net LV_SDA)	Qwiic I2C
44	SCL	Qwiic (1 mm JST-SH) pad 4: SCL through the logic level converter (fab net LV_SCL)	Qwiic I2C

Buses

Bus	Signals	Pins	Voltage	Note
I2C ×2	SDA, SCL	SDA, SCL	3.3 V at the Qwiic socket, 5 V or 3.3 V at the header depending on the I/O switch V	SDA is A4/PC4 and SCL is A5/PC5. The same two nets reach the analog header, the high digital header, the 2x3 ISP header's neighbours and the Qwiic socket; at the socket they are the level-converted LV_SDA/LV_SCL nets. Jumpers QW1 (A4) and QW2 (A5) are fitted closed, and cutting them takes the logic level converters off those header pins.
SPI ×1	SCK, CIPO, COPI	SCK, CIPO, COPI	5 V or 3.3 V, following the I/O switch V	D13 = SCK/PB5, D12 = CIPO/PB4, D11 = COPI/PB3, with D10/PB2 as the usual chip select. The 2x3 ISP header brings out the same three lines plus RESET, VCC and GND.
UART ×1	RXD, TXD	RX<-0, TX->1	5 V or 3.3 V, following the I/O switch V	D0/PD0 is RXD and D1/PD1 is TXD, and both are shared with the CH340G USB-serial converter, so anything wired to them interferes with sketch uploads.

Power

Input	7-15 V DC on the barrel jack, or 5 V over USB-C
Input range	7-15 V (barrel jack); 5 V (USB-C)

SparkFun publishes no board-level current draw. The board carries extra decoupling capacitance on the supply, which SparkFun says increases the sensitivity of the ADC readings.

Outputs

Rail	Rating	Note
5 V	5 V V	LM1117 adjusted to 5 V; the rail the ATmega328P runs from. Protected by a built-in resettable PTC fuse rated 5 V/2 A, which the BYP jumper can bypass with solder.
3.3 V	3.3 V V, 600 mA max	AP2112 regulator, up to 600 mA, intended to daisy-chain Qwiic boards and sensors, with thermal and reverse-circuit protection.

Notes

Pin numbers are this entry's own sequence 1-44 across the connectors, because every connector numbers its own pads from 1: power header JP10 is pads 1-8, analog JP13 is 1-6, low digital JP11 is 1-8, high digital JP2 is 10 pads named 1A-10A (the A suffix is the through-hole pad of a combined TH/SMD footprint, and the row runs from SCL at 1A to D8 at 10A, the reverse of the silk order), A6/A7 are J1 pads 1-2, the ISP header is J2 pads 1-6 and Qwiic is J4 pads 1-4. Each pad's description names its connector and fab pad so the join survives the renumbering, and the numbers come from the Eagle fab file (Hardware/RedBoard_Plus.brd in SparkFun's GitHub repo), whose nets also confirm every function here. The graphical datasheet is the source for the silk labels and the port/PWM/ADC functions; the fab file numbers nothing in silk text, so the labels were not read from artwork. Two vendor statements to flag: the product page and feature list both name a CH340G, while the documentation section links 'How to Install CH340C Drivers'; and SparkFun's feature list counts 22 digital I/O including the six analog-capable A0-A5, while A6 and A7 are analog-only. The Qwiic socket is 3.3 V only, so a 5 V-only I2C device needs a shifter even with the I/O switch set to 5 V. The board ships with no headers soldered and has PTH holes alongside the female header positions for direct wiring.

AI context

Dense context for pasting into a model prompt — addresses, pinout, voltages, tolerances and the vendor's reference circuit.

PART: SparkFun RedBoard Plus, SKU DEV-18158: an Arduino Uno R3 compatible board built on a Microchip ATmega328P with the Optiboot (UNO) bootloader, a 16 MHz resonator, 32 kB flash, 1 kB EEPROM, 2 kB SRAM, 22 digital I/O (6 PWM), 8 analog inputs (10-bit ADC) and PWM timers that are 8-bit. USB-C (reversible, through-hole anchored) goes to a CH340G USB-serial converter; the board adds a Qwiic connector, 3.3 V level translation on the I2C pair, a 2x3 ISP header, and PTH holes beside every female header for soldering wires.
ADDRESSES: none. The ATmega328P is the I2C host here, not a device, so the board has no I2C address of its own; the address on SDA/SCL is whatever Qwiic device is attached. SDA is A4/PC4 and SCL is A5/PC5, and those two header pins are wired through the level converter to the Qwiic socket by default.
PINOUT: pads 1-8 are the power header (fab JP10 pads 1-8): 1 VIN, 2 GND, 3 GND, 4 5V, 5 3.3V, 6 RESET, 7 IOREF, 8 NC (no net). Pads 9-14 are the analog header (JP13 pads 1-6): 9 A0/PC0/ADC0, 10 A1/PC1/ADC1, 11 A2/PC2/ADC2, 12 A3/PC3/ADC3, 13 A4/PC4/ADC4/SDA, 14 A5/PC5/ADC5/SCL. Pads 15-22 are the low digital header (JP11 pads 1-8): 15 RX<-(D0/PD0/RXD), 16 TX->(D1/PD1/TXD), 17 D2/PD2, 18 D3/PD3, 19 D4/PD4, 20 D5/PD5, 21 D6/PD6, 22 D7/PD7. Pads 23-32 are the high digital header (JP2 pads 1A-10A, which run opposite the silk order): 23 SCL, 24 SDA, 25 AREF, 26 GND, 27 D13/PB5/SCK, 28 D12/PB4/CIPO, 29 D11/PB3/COPI, 30 D10/PB2/CS, 31 D9/PB1, 32 D8/PB0. Pads 33-34 are A6 and A7 (J1), analog-only. Pads 35-40 are the 2x3 ISP header (J2): CIPO, VCC, SCK, COPI, RESET, GND. Pads 41-44 are the Qwiic socket (J4): GND, 3.3V, SDA, SCL. The numbers are this entry's sequence across the connectors because each connector numbers its own pads from 1, and each pad's description names the connector and its fab pad.
SUPPLY: 7 V to 15 V DC on the barrel jack, or 5 V over USB-C. An LM1117 adjusted to 5 V makes the 5 V rail and an AP2112 makes 3.3 V at up to 600 mA for daisy-chained Qwiic boards, with thermal and reverse-circuit protection; the resettable PTC fuse is 5 V/2 A (up from 500 mA on the RedBoard).
LOGIC: 5 V by default. The I/O voltage switch (SparkFun calls it the Red Squirrel switch) sets the GPIO, IOREF and VCC rails to 3.3 V or 5 V, so a 3.3 V shield or sensor can be protected by moving it. The ATmega328P's absolute maximum VCC is 6 V; per pin the absolute maximum is 40 mA and the recommended current is 20 mA, with 200 mA the chip's total maximum, so a pin driven past 40 mA is outside the vendor's rating and damages the port driver.
REFERENCE CIRCUIT: the A4 and A5 header pins are tied to the I2C level converter through jumpers (QW1 on A4, QW2 on A5) fitted closed by default; cut them to use A4/A5 as plain analog inputs or to take the converters off those pins. The board carries extra decoupling capacitance on the supply so ADC readings are less sensitive to noise. The BYP jumper bypasses the PTC fuse when solder is added. USB D+/D- are also broken out as solder pads on the back of the board for an external USB connection.
TRAPS: A4/A5 only reach the ADC cleanly after the QW1/QW2 jumpers are cut, because by default they pass through the level converter; A6 and A7 are analog inputs with no digital function; the I/O switch moves every I/O rail at once, so tape it if it must not move; UART is D0/D1 and is shared with the CH340G, so it must be free to upload; the product page and feature list both say CH340G while the documentation link offers CH340C drivers; the header pads are female sockets, with unlabelled PTH holes alongside for soldering.

Provenance

Every figure on this page was read from the 5 sources below and last checked on Oct 23, 2026.