Verified 2026-10

sparkfun MIMXRT1062DVL6B Teensy 4.0

PJRC's 600 MHz Cortex-M7 Teensy 4.0 (1.4 x 0.7 in, micro-USB): 1984 KB usable QSPI flash, 1 MB RAM, 40 numbered 3.3 V pads with 14 analog inputs, 7 serial ports, 3 SPI, 3 I2C and 3 CAN, priced at $23.80 by SparkFun.

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Logic level3.3 V

Part & documents

Headline part	MIMXRT1062DVL6B
Data sheet	MIMXRT1062DVL6B data sheet →
Source	www.sparkfun.com/teensy-4-0.html →

Specs

MCU	NXP MIMXRT1062DVL6B (i.MX RT1062, Cortex-M7, 600 MHz, 1 MB RAM, 144-pin package)
Clock	600 MHz
Flash	1.9375 MB
RAM	1024 KB
I/O	40 digital, 14 analog, 27 PWM

PJRC's tech-specs table: 40 digital I/O of which 24 are breadboard-friendly, 14 analog inputs on 2 converters at 10 usable bits, 27 PWM outputs, 40 interrupts. 1080 bytes of EEPROM are emulated in flash. Analog inputs are A0-A13 on pads 14-23 and 24-27.

Pinout

40 pads, as the vendor numbers them.

#	Name	Function	Signals
0	RX1	Front edge pad 0 (lower row, left to right): RX1 - Serial1 RX1, CAN2 CRX2, PWM	Serial1 RX1, CAN2 CRX2, PWM
1	TX1	Front edge pad 1 (lower row, left to right): TX1 - Serial1 TX1, CAN2 CTX2, PWM	Serial1 TX1, CAN2 CTX2, PWM
2	OUT2	Front edge pad 2 (lower row, left to right): OUT2 - I2S2 OUT2, PWM	I2S2 OUT2, PWM
3	LRCLK2	Front edge pad 3 (lower row, left to right): LRCLK2 - I2S2 LRCLK2, PWM	I2S2 LRCLK2, PWM
4	BCLK2	Front edge pad 4 (lower row, left to right): BCLK2 - I2S2 BCLK2, PWM	I2S2 BCLK2, PWM
5	IN2	Front edge pad 5 (lower row, left to right): IN2 - I2S2 IN2, PWM	I2S2 IN2, PWM
6	OUT1D	Front edge pad 6 (lower row, left to right): OUT1D - I2S1 OUT1D, PWM	I2S1 OUT1D, PWM
7	RX2	Front edge pad 7 (lower row, left to right): RX2 - Serial2 RX2, I2S1 OUT1A, PWM	Serial2 RX2, I2S1 OUT1A, PWM
8	TX2	Front edge pad 8 (lower row, left to right): TX2 - Serial2 TX2, I2S1 IN1, PWM	Serial2 TX2, I2S1 IN1, PWM
9	OUT1C	Front edge pad 9 (lower row, left to right): OUT1C - I2S1 OUT1C, PWM	I2S1 OUT1C, PWM
10	CS	Front edge pad 10 (lower row, left to right): CS - SPI0 CS, MQS right, PWM	SPI0 CS, MQS right, PWM
11	MOSI	Front edge pad 11 (lower row, left to right): MOSI - SPI0 MOSI, CAN1 CTX1 (alternate), PWM	SPI0 MOSI, CAN1 CTX1 (alternate), PWM
12	MISO	Front edge pad 12 (lower row, left to right): MISO - SPI0 MISO, MQS left, PWM	SPI0 MISO, MQS left, PWM
13	(LED)	Front edge pad 13 (upper row, printed right to left): (LED) - on-board LED, SPI0 SCK, CAN1 CRX1 (alternate), PWM	on-board LED, SPI0 SCK, CAN1 CRX1 (alternate), PWM
14	A0	Front edge pad 14 (upper row, printed right to left): A0 - analog A0, Serial3 TX3, S/PDIF output, PWM	analog A0, Serial3 TX3, S/PDIF output, PWM
15	A1	Front edge pad 15 (upper row, printed right to left): A1 - analog A1, Serial3 RX3, S/PDIF input, PWM	analog A1, Serial3 RX3, S/PDIF input, PWM
16	A2	Front edge pad 16 (upper row, printed right to left): A2 - analog A2, Wire1 SCL1, Serial4 RX4	analog A2, Wire1 SCL1, Serial4 RX4
17	A3	Front edge pad 17 (upper row, printed right to left): A3 - analog A3, Wire1 SDA1	analog A3, Wire1 SDA1
18	A4	Front edge pad 18 (upper row, printed right to left): A4 - analog A4, Wire SDA0, PWM	analog A4, Wire SDA0, PWM
19	A5	Front edge pad 19 (upper row, printed right to left): A5 - analog A5, Wire SCL0, PWM	analog A5, Wire SCL0, PWM
20	A6	Front edge pad 20 (upper row, printed right to left): A6 - analog A6, Serial5 TX5, I2S1 LRCLK1	analog A6, Serial5 TX5, I2S1 LRCLK1
21	A7	Front edge pad 21 (upper row, printed right to left): A7 - analog A7, Serial5 RX5, I2S1 BCLK1	analog A7, Serial5 RX5, I2S1 BCLK1
22	A8	Front edge pad 22 (upper row, printed right to left): A8 - analog A8, CAN1 CTX1, PWM	analog A8, CAN1 CTX1, PWM
23	A9	Front edge pad 23 (upper row, printed right to left): A9 - analog A9, CAN1 CRX1, I2S1 MCLK1, PWM	analog A9, CAN1 CRX1, I2S1 MCLK1, PWM
24	A10	Underside pad 24 (even-numbered column): A10 - analog A10, Serial6 TX6, Wire2 SCL2, PWM	analog A10, Serial6 TX6, Wire2 SCL2, PWM
25	A11	Underside pad 25 (odd-numbered column): A11 - analog A11, Serial6 RX6, Wire2 SDA2, PWM	analog A11, Serial6 RX6, Wire2 SDA2, PWM
26	A12	Underside pad 26 (even-numbered column): A12 - analog A12, SPI1 MOSI1	analog A12, SPI1 MOSI1
27	A13	Underside pad 27 (odd-numbered column): A13 - analog A13, SPI1 SCK1	analog A13, SPI1 SCK1
28	RX7	Underside pad 28 (even-numbered column): RX7 - Serial7 RX7, PWM	Serial7 RX7, PWM
29	TX7	Underside pad 29 (odd-numbered column): TX7 - Serial7 TX7, PWM	Serial7 TX7, PWM
30	CRX3	Underside pad 30 (even-numbered column): CRX3 - CAN3 CRX3	CAN3 CRX3
31	CTX3	Underside pad 31 (odd-numbered column): CTX3 - CAN3 CTX3	CAN3 CTX3
32	OUT1B	Underside pad 32 (even-numbered column): OUT1B - I2S1 OUT1B, PWM	I2S1 OUT1B, PWM
33	MCLK2	Underside pad 33 (odd-numbered column): MCLK2 - I2S2 MCLK2, PWM	I2S2 MCLK2, PWM
34	DAT1	Underside pad 34 (single lower column): DAT1 - SD card DAT1, SPI2 MISO2, PWM	SD card DAT1, SPI2 MISO2, PWM
35	DAT0	Underside pad 35 (single lower column): DAT0 - SD card DAT0, SPI2 MOSI2, PWM	SD card DAT0, SPI2 MOSI2, PWM
36	CLK	Underside pad 36 (single lower column): CLK - SD card CLK, SPI2 CS2, PWM	SD card CLK, SPI2 CS2, PWM
37	CMD	Underside pad 37 (single lower column): CMD - SD card CMD, SPI2 SCK2, PWM	SD card CMD, SPI2 SCK2, PWM
38	DAT3	Underside pad 38 (single lower column): DAT3 - SD card DAT3, Serial5 RX5 as printed, PWM	SD card DAT3, Serial5 RX5 as printed, PWM
39	DAT2	Underside pad 39 (single lower column): DAT2 - SD card DAT2, Serial5 TX5 as printed, PWM	SD card DAT2, Serial5 TX5 as printed, PWM

Buses

Bus	Signals	Pins	Voltage	Note
I2C ×3	SDA, SCL	SDA0/SCL0, SDA1/SCL1, SDA2/SCL2	3.3 V V	Wire is pads 18 (SDA0) and 19 (SCL0) on the front edge; Wire1 is 17 (SDA1) and 16 (SCL1); Wire2 is 25 (SDA2) and 24 (SCL2) on the underside. No address is attributed to the board - it has no I2C device of its own, and no pull-up value is published in the sources behind this entry.
SPI ×3	SCK, MISO, MOSI, CS	SCK, MISO, MOSI, CS	3.3 V V	SPI0 on pads 13 (SCK), 12 (MISO), 11 (MOSI), 10 (CS); SPI1 on 27 (SCK1) and 26 (MOSI1), with 39 (MISO1) and 38 (CS1) printed on the 4.1 card but not on the 4.0 card; SPI2 shares the SD-card pads 34-37 as MISO2/MOSI2/CS2/SCK2.
UART ×7	RX, TX	RX1/TX1, RX2/TX2, RX3/TX3, RX4/TX4, RX5/TX5, RX6/TX6, RX7/TX7	3.3 V V	Serial1 on 0/1, Serial2 on 7/8, Serial3 on 15/14, Serial4 on 16/17, Serial5 on 21/20, Serial6 on 25/24, Serial7 on 28/29. PJRC's tech-specs table states 7 serial ports, all with FIFOs.
CAN ×3	CRX, CTX	CRX1/CTX1, CRX2/CTX2, CRX3/CTX3	3.3 V V	CAN1 on pads 23 (CRX1) and 22 (CTX1), with alternates on 13 and 11; CAN2 on 0 (CRX2) and 1 (CTX2); CAN3 on 30 (CRX3) and 31 (CTX3). PJRC states one of the three supports CAN-FD. A transceiver is not on the board.

Power

Input	3.6-5.5 V on VIN, or 5 V over USB micro-B on VUSB
Input range	3.6-5.5 V (VIN); 5 V (VUSB)
Typical draw	100 mA

SparkFun states about 100 mA when running at 600 MHz. PJRC rates each digital output at 10 mA. VIN and VUSB are joined by a cuttable pair of pads.

Outputs

Rail	Rating	Note
3.3 V	3.3 V V, 250 mA max	The 3.3V pad is an output, capped at 250 mA by PJRC's card; the MIMXRT1062 and the flash run from it.

Notes

PJRC prints numbers on the 40 signal pads and on none of the power pads, so `pins[]` holds 0-39 only; VIN, GND, 3.3V, On/Off, Program, VBAT and the interleaved underside GND/3.3V are described in ai_context and are unnumbered. Pad numbers and labels both come from PJRC's own front/back cards, joined by the cards' column geometry and checked against the card's known-good anchors (RX1=0, TX1=1, CS=10, MOSI=11, MISO=12, A0-A9=14-23, SCL2=24, SDA2=25, RX7=28, TX7=29). The headline part is the MIMXRT1062DVL6B on SparkFun's page; the data-sheet link is PJRC's own copy of NXP's IMXRT1060CEC rev 4 family data sheet (nxp.com/docs/en/data-sheet/IMXRT1060CEC.pdf returns 404, PJRC's mirror returns application/pdf). SparkFun's own title carries no chip name, which is why `part` is lifted out of its prose and the name reads `sparkfun MIMXRT1062DVL6B Teensy 4.0`.

AI context

Dense context for pasting into a model prompt — addresses, pinout, voltages, tolerances and the vendor's reference circuit.

PART: NXP MIMXRT1062DVL6B, an i.MX RT1062 "Crossover" MCU - Cortex-M7 at 600 MHz (PJRC rates it overclockable to 912 MHz), 144-pin package, with a 32 and 64-bit FPU, 65536-byte cache and 512 KB of the 1024 KB RAM as single-cycle tightly coupled memory. The Teensy 4.0 board is 1.4 x 0.7 in and carries NXP's own flash in a QSPI W25Q16JV: 1984 KB usable of 2 MB, 64 KB reserved for EEPROM emulation (1080 bytes of emulated EEPROM).
I2C ADDRESS: none. The board carries no I2C device; all three ports are host-only - Wire on pads 18 (SDA0) and 19 (SCL0), Wire1 on 17 (SDA1) and 16 (SCL1), Wire2 on 25 (SDA2) and 24 (SCL2). Any address on the bus belongs to whatever is plugged in, not to this board.
PINOUT: 40 numbered solder pads, 0-39, all 3.3 V logic. Front component side, upper row printed 23 down to 13 left to right, lower row 0 to 12 left to right: 0 RX1/CAN2-CRX2, 1 TX1/CAN2-CTX2, 2 I2S2 OUT2, 3 LRCLK2, 4 BCLK2, 5 IN2, 6 OUT1D, 7 RX2/OUT1A, 8 TX2/IN1, 9 OUT1C, 10 SPI0 CS/MQSR, 11 SPI0 MOSI/CAN1-CTX1 alternate, 12 SPI0 MISO/MQSL, 13 on-board LED/SCK/CAN1-CRX1 alternate, 14 A0/TX3/S-PDIF out, 15 A1/RX3/S-PDIF in, 16 A2/SCL1/RX4, 17 A3/SDA1, 18 A4/SDA0, 19 A5/SCL0, 20 A6/TX5/LRCLK1, 21 A7/RX5/BCLK1, 22 A8/CTX1, 23 A9/CRX1/MCLK1. Underside: 24 A10/TX6/SCL2, 25 A11/RX6/SDA2, 26 A12/MOSI1, 27 A13/SCK1, 28 RX7, 29 TX7, 30 CRX3, 31 CTX3, 32 OUT1B, 33 MCLK2, then a single column 34 DAT1/MISO2, 35 DAT0/MOSI2, GND, 36 CLK/CS2, 3.3V, 37 CMD/SCK2, 38 DAT3/RX5, 39 DAT2/TX5.
UNNUMBERED PADS: one end carries VIN, GND and 3.3V; the other carries On/Off, Program, GND, 3.3V and VBAT, and the underside column interleaves a GND between pads 35 and 36 and a 3.3V between 36 and 37. PJRC prints no number on any of these, so they are described here rather than numbered into the pin map.
SUPPLY: VIN accepts 3.6 to 5.5 V; USB micro-B supplies 5 V on VUSB. The 3.3V pad is an output, 250 mA maximum, not an input. The board draws about 100 mA at 600 MHz. PJRC rates each digital output at 10 mA.
LOGIC LEVEL: 3.3 V only. The signal pads are not 5 V tolerant - do not apply more than 3.3 V to any pin except VIN or VUSB. A 5 V sensor output taken straight onto a pad over-volts the MIMXRT1062's GPIO and there is no series resistor to save it.
REFERENCE CIRCUIT: VIN and VUSB are joined on the board by a pair of solder pads; PJRC says to cut between them when the board is powered from an external supply while USB is also attached. VBAT takes a 3 V coin cell for the real-time clock and power-management features. PJRC publishes no pull-up or decoupling value in the sources behind this entry, so none is recorded - an I2C add-on must bring its own pull-ups.
TRAPS: pad 13 also carries the on-board LED, and its red LED doubles as the loading status (dim = ready, bright = writing, blinking = no USB). The CAN1 names are printed twice: CRX1/CTX1 as the primary pair on pads 23/22 and faded as alternates on pads 13/11, which are also SPI0 SCK/MOSI. Pads 34-39 are the SD card's 4-bit SDIO lines (DAT0-DAT3, CLK, CMD) and SPI2's MISO2/MOSI2/CS2/SCK2 at the same time, and pads 38/39 additionally print RX5/TX5 even though pads 21/20 already print RX5/TX5 - the card contradicts itself and both printings are recorded. Wire2 exists only on the underside pads 24/25; the front pads 16-19 are Wire1 and Wire. PJRC's card marks PWM beside 32 pads while its tech-specs table states 27 PWM outputs; both figures are recorded and neither is corrected.

Provenance

Every figure on this page was read from the 5 sources below and last checked on Oct 26, 2026.